Difference between revisions of "Silicon Labs EFR32xG25"
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===Reset=== |
===Reset=== |
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*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The devices uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| + | ==Limitations== |
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| + | === Security === |
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| + | See: [[Silicon Labs EFx32 Series 2#Debug lock | Silicon Labs EFx32 Series 2]] article. |
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| + | === Secure boot === |
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| + | See: [[Silicon Labs EFx32 Series 2#Secure boot specific | Silicon Labs EFx32 Series 2]] article. |
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==Evaluation Boards== |
==Evaluation Boards== |
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Revision as of 16:26, 10 October 2023
The Silicon Labs EFR32xG25 are wireless SoCs based on Cortex-M33 microcontrollers. These MCUs are part of the EFx32 Series 2 devices.
Contents
EFx32 Series 2 specifics
Please refer to the Silicon Labs EFx32 Series 2 article.
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 1920 KB | 
|
| User Data | 0x0FE00000 | 1 KB |
|
Watchdog Handling
- The device has 2 Watchdogs, they are feed during programming, if they are enabled.
Device Specific Handling
Reset
- The devices uses normal Cortex-M reset, no special handling necessary, like described here.
Limitations
Security
See: Silicon Labs EFx32 Series 2 article.
Secure boot
See: Silicon Labs EFx32 Series 2 article.
Evaluation Boards
- Silicon Labs ERF32xG25 evaluation board: https://wiki.segger.com/Silicon_Labs_BRD4271A
Example Application
- Silicon Labs ERF32xG25 evaluation board: https://wiki.segger.com/Silicon_Labs_BRD4271A#Example_Project
