Difference between revisions of "Synergy"
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*System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
*System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
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*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
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| + | *ICLK = 8MHz * 1 / 16 = 500 kHz CPU clock |
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| − | |||
| − | + | *TRCLK = ICLK * 1 / 2 = 250 kHz Trace / SWO clock |
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| − | TRCLK = ICLK * 1 / 2 = 250 kHz Trace / SWO clock |
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CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 kHz * 16 / 2 = 4 MHz |
CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 kHz * 16 / 2 = 4 MHz |
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| Line 18: | Line 17: | ||
*System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
*System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock) |
||
*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
*Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2 |
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| + | *ICLK = 8MHz * 1 / 4 = 2 MHz CPU clock |
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| − | |||
| − | + | *TRCLK = ICLK * 1 / 2 = 1 MHz Trace / SWO clock |
|
| − | TRCLK = ICLK * 1 / 2 = 1 MHz Trace / SWO clock |
||
CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 2 MHz * 4 / 2 = 4 MHz |
CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 2 MHz * 4 / 2 = 4 MHz |
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Revision as of 16:03, 8 February 2017
Using SWO on Synergy Devices
In general, the J-Link DLL expects the trace clock to be equal to the CPU clock. As the Synergy device series allows to enable a pre-scaler which is valid for trace clock only, this assumption may be incorrect resulting in invalid SWO data are read. To make sure that the J-Link DLL behaves as expected, please make sure to not enter the actual CPU clock but the CPU clock multiplied with the ICKdivider configured in the System Clock Division Control Register (SCKDIVCR) divided by the trace clock divider configured in the Trace Clock Control Regigster (TRCKCR).
Example (S3A7)
- MOCO (8MHz)
- System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 16
- System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock)
- Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2
- ICLK = 8MHz * 1 / 16 = 500 kHz CPU clock
- TRCLK = ICLK * 1 / 2 = 250 kHz Trace / SWO clock
CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 500 kHz * 16 / 2 = 4 MHz
Example (S7G2)
- MOCO (8MHz)
- System Clock Division Control Register (SCKDIVCR[ICK[2:0]]): 0x4 --> * 1 / 4
- System Clock Source Control Register (SCKSCR[CKSEL[2:0]]): 0x1 --> MOCO selected as source for the ICLK (System Clock) and TRCLK (Trace Clock)
- Trace Clock Control Register (TRCKCR[TRCK[3:0]]): 0x1 --> /2
- ICLK = 8MHz * 1 / 4 = 2 MHz CPU clock
- TRCLK = ICLK * 1 / 2 = 1 MHz Trace / SWO clock
CPU clock to be entered in the IDE project = ICLK * ICKdivider / TRCKdivider = 2 MHz * 4 / 2 = 4 MHz
