Difference between revisions of "Syntacore SCR1"
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| + | The Syntacore SCR1 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip/scr1 Syntacore]. |
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__TOC__ |
__TOC__ |
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| + | = Requirements = |
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| + | * A current J-Link model with RISC-V support |
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| + | * [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V6.44d or later. Older J-Link software versions will not work. |
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| + | * The SCR1 device selection is supported since V6.44d |
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| + | = RTT support = |
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| − | <red>TBD!!!!!!!!!!!!!!!!!</red> |
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| + | As the core does not support System Bus Access (SBA), RTT is '''not''' supported for this core. |
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| + | = HSS access = |
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| − | This article describes specifics for the SiFive Arty FPGA Dev Kit. |
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| + | As the core does not support System Bus Access (SBA), HSS is '''not''' supported for this core. |
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| + | = Limitations = |
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| − | == Preparing for J-Link == |
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| + | * When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. '''This is not a limitation of J-Link but of the Syntacore SCR1''' |
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| − | Syntacore provides a reference FPGA bistream for the Digilent ARTY FPGA dev kit, which allows to implement a RISC-V core. The Digilent ARTY FPGA dev kit does not come with a standard debug connector but populates the debug JTAG signals on the JD connector of the eval board. Therefore, it needs to be manually wired in case J-Link shall be connected to it. |
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| + | = Example projects = |
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| − | In the following, it is described how the pins of JD connector on the ARTY board needs to be wired to J-Link. All pins of the J-Link side refer to the standard 0.1" 20-pin connector of J-Link. |
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| + | [[File:Syntacore_SCR1_Arty_ES.zip]] |
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| + | Requires [https://www.segger.com/downloads/embedded-studio/ SEGGER Embedded Studio for RISC-V] V4.12 or later |
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| − | {| class="wikitable" |
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| − | |+Wiring connection |
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| − | ! Pin JD (ARTY) |
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| − | ! Pin J-Link |
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| − | ! Description |
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| − | |- |
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| − | |7 |
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| − | |13 |
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| − | |TDO |
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| − | |- |
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| − | |3 |
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| − | |3 |
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| − | |nTRST |
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| − | |- |
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| − | |4 |
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| − | |9 |
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| − | |TCK |
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| − | |- |
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| − | |8 |
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| − | |5 |
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| − | |TDI |
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| − | |- |
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| − | |10 |
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| − | |7 |
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| − | |TMS |
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| − | |- |
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| − | |9 |
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| − | |15 |
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| − | |nRESET |
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| − | |- |
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| − | |11 |
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| − | |4 |
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| − | |GND |
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| − | |- |
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| − | |12 |
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| − | |1 |
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| − | |VTref |
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| − | |} |
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| + | Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000 |
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| − | '''Note:''' The pins on the JD connector are numbered as follows: |
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| − | {| class="wikitable" |
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| − | |- |
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| − | |6 |
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| − | |5 |
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| − | |4 |
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| − | |3 |
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| − | |2 |
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| − | |1 |
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| − | |- |
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| − | |12 |
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| − | |11 |
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| − | |10 |
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| − | |9 |
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| − | |8 |
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| − | |7 |
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| − | |} |
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| + | == Embedded Studio == |
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| − | <Photo> |
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| + | * Please make sure to install SEGGER Embedded Studio first |
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| + | * Then install the J-Link software package |
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| + | * At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio |
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| + | * Please perform the update |
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| − | + | = Available eval boards = |
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| + | The following eval boards are available: |
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| − | TBD |
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| + | * [[Syntacore SCR1 SDK Arty | SCR1 SDK Arty (ARTY board)]] |
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| − | '''Before continuing, make sure that you have J-Link software package Vxxx or later installed''': [https://www.segger.com/downloads/jlink/ Download J-Link software package] |
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| + | <references/> |
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| − | == Minimum J-Link hardware requirements == |
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| − | Please note that RISC-V is not supported by older J-Link hardware models / revisions. For an overview about which models / revisions support RISC-V: [[Software and Hardware Features Overview | List]] |
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Latest revision as of 13:41, 19 July 2021
The Syntacore SCR1 is a 32-bit (RV32) core, designed by Syntacore.
Contents
Requirements
- A current J-Link model with RISC-V support
- J-Link software V6.44d or later. Older J-Link software versions will not work.
- The SCR1 device selection is supported since V6.44d
RTT support
As the core does not support System Bus Access (SBA), RTT is not supported for this core.
HSS access
As the core does not support System Bus Access (SBA), HSS is not supported for this core.
Limitations
- When debugging on the Syntacore SCR1, the max. JTAG speed that can be used is 1/12 of the CPU speed, so usually fJTAG has to be <= 2 MHz. Speeds above this limit will result in unstable operation of the debug interface on the device. The device sometimes simply returns garbage status info and data on debug module accesses. This is not a limitation of J-Link but of the Syntacore SCR1
Example projects
File:Syntacore SCR1 Arty ES.zip
Requires SEGGER Embedded Studio for RISC-V V4.12 or later
Downloads a simple Cnt++ loop into the 64 TCM @ 0xF0000000
Embedded Studio
- Please make sure to install SEGGER Embedded Studio first
- Then install the J-Link software package
- At the end of the software package installation, you will be asked if you want to update SEGGER Embedded Studio
- Please perform the update
Available eval boards
The following eval boards are available:
