Difference between revisions of "TI AM335x"
(→RTT) |
|||
| (2 intermediate revisions by 2 users not shown) | |||
| Line 1: | Line 1: | ||
| + | [[Category:Device families]] |
||
__TOC__ |
__TOC__ |
||
= RTT = |
= RTT = |
||
* Since V6.98b of the J-Link software, RTT can be used out-of-the-box. |
* Since V6.98b of the J-Link software, RTT can be used out-of-the-box. |
||
| − | * When using RTT control block auto-detection, J-Link searches in the internal SRAM @ 0x40300000 - 0x4030FFFF (64 |
+ | * When using RTT control block auto-detection, J-Link searches in the internal SRAM @ 0x40300000 - 0x4030FFFF (64 KiB) for an RTT control block |
* The internal SRAM located at 0x402F0400 cannot be used for RTT as it is not accessible by the AHB-AP via which RTT accesses are performed. |
* The internal SRAM located at 0x402F0400 cannot be used for RTT as it is not accessible by the AHB-AP via which RTT accesses are performed. |
||
| − | * As the TI AM335x series implements cache, please refer to the [[RTT#RTT_on_Cortex-A_targets| RTT wiki article]] |
+ | * As the TI AM335x series implements cache, please refer to the RTT wiki article for further instructions / information: [[RTT#RTT_on_Cortex-A_targets| RTT wiki article]] |
Latest revision as of 14:36, 15 May 2024
Contents
RTT
- Since V6.98b of the J-Link software, RTT can be used out-of-the-box.
- When using RTT control block auto-detection, J-Link searches in the internal SRAM @ 0x40300000 - 0x4030FFFF (64 KiB) for an RTT control block
- The internal SRAM located at 0x402F0400 cannot be used for RTT as it is not accessible by the AHB-AP via which RTT accesses are performed.
- As the TI AM335x series implements cache, please refer to the RTT wiki article for further instructions / information: RTT wiki article
