Difference between revisions of "Xilinx Zynq UltraScalePlus"
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J-Link software [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack V6.45c] or later is required. Older versions will not work. |
J-Link software [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack V6.45c] or later is required. Older versions will not work. |
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| − | In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with ''XCZU..._R5_0'' must be selected. For a list of supported device names, please refer to the [https://www.segger.com/downloads/supported-devices.php list of supported devices] |
+ | In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with ''XCZU..._R5_0'' must be selected. For a list of supported device names, please refer to the [https://www.segger.com/downloads/supported-devices.php list of supported devices] on the SEGGER website. |
Revision as of 18:11, 25 March 2019
This article describes device specifics of the Xilinx Zynq UltraScale+ series devices.
Families
The Zynq UltraScale+ series consists of the following families:
- Zynq UltraScale+ CG (2x Cortex-A53, 2x Cortex-R5)
- Zynq UltraScale+ DR (4x Cortex-A53, 2x Cortex-R5)
- Zynq UltraScale+ EG (4x Cortex-A53, 2x Cortex-R5)
- Zynq UltraScale+ EV (4x Cortex-A53, 2x Cortex-R5)
Debugging
Debugging the Cortex-R5
Software requirements
J-Link software V6.45c or later is required. Older versions will not work.
In order to connect to and debug one of the available Cortex-R5 on the UltraScale+ series, an UltraScale+ device with XCZU..._R5_0 must be selected. For a list of supported device names, please refer to the list of supported devices on the SEGGER website.
