i.MXRT1050
NXP's iMXRT105x family features a Cortex-M7 core without internal flash but with support for both, QSPI and HyperFlash through a so called FLEXSPI controller. NXP's official evaluation board, the MIMXRT1050 EVK is shipped with a 512Mbit Hyper Flash device by default. Alternatively, a QSPI flash can be mounted but several board modifications (removing the hyper flash, adding resistors, etc...) are required. As both flashes are accessed through the same memory mapped address space, either the HyperFlash or the QSPI flash RAMCode needs to be used for memory accesses to this area. Please find below further information how to enable the desired flash algorithm (RAMCode).
Hyper Flash
By default, the Hyper Flash algorithm is selected by the J-Link software. No additional steps are required.
QSPI flash
To enable the QSPI flash support in the J-Link software, the JLinkDevices.xml needs to be modified. For further information regarding the JLinkDevices.xml, please refer to the Open Flashloader chapter in the J-Link User Manual (UM08001).
- Open the JLinkDevices.xml
- Search the desired iMXRT <Device> entry
- Change JLinkScriptFile="Devices/NXP/iMXRT105x/NXP_iMRXT105x_HyperFlash.pex" to JLinkScriptFile="Devices/NXP/iMXRT105x/NXP_iMRXT105x_QSPI.pex"
- Change Loader="Devices/NXP/iMXRT105x/NXP_iMXRT105x_HyperFlash.elf" to Loader="Devices/NXP/iMXRT105x/NXP_iMXRT105x_QSPI.elf"
- Save JLinkDevices.xml
From now, the J-Link software uses the QSPI RAMCode instead of the HyperFlash RAMCode for the flash download.
