i.MXRT600
This article covers the NXP i.MXRT600 MCU family devices.
Tracing on MIMXRT600 series
This section describes how to get started with trace on the NXP MIMXRT600 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).
Note:
- The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
- The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace.
- In order to rebuild the sample project, SEGGER Embedded Studio can be used.
- All examples are shipped with a compiled .JLinkScriptfile (.pex), should you need the original source it can be requested at support@segger.com.
Tracing on NXP MIMXRT685S
Minimum requirements
In order to use trace on the NXP MIMXRT685S MCU devices, the following minimum requirements have to be met:
- J-Link software version V6.80 or later
- Ozone V3.10j or later (if streaming trace and / or the sample project from below shall be used)
- J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace
- J-Link Plus V10 or later for TMC/ETB trace
Streaming trace
The project has been tested with the minimum requirements mentioned above and a NXP X-MIMXRT685-EVK.
Example project: NXP_iMXRT685_Trace_Example.zip
Trace buffer (TMC/ETB)
Example Project: TBD
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
QSPI support
The RT600 does not come with internal flash but with external flash connected to the FlexSPI bus, only. The external FlexSPI controller allows to connect several different flash types like QSPI, HyperFlash and Octaflash. Furthermore, the external flash can be connected to different pin / ports of the FlexSPI controller which makes a auto-detection very difficult thus a out-of-the-box solution which works for all setups is kind of impossible. For that reason, the J-Link software supports the evaluation board setup, only. Other setups may work but without any warranty or guarantee from SEGGER. If you are working with a different setup and looking for support for this setup, please get in touch with SEGGER.
Supported QSPI setup
- J-Link Software: >= V6.62d
- Hardware: NXP X-MIMXRT685-EVK
- Flash: MX25UM51345GXDI00 (octaflash) connected to FlexSPI port B
| Signal Name | GPIO name | IO function |
|---|---|---|
| QSPI_B_CS0 | PIO2_19 | FLEXSPI0B_SS0_N |
| QSPI_B_SCK | PIO1_29 | FLEXSPI0B_SCLK |
| QSPI_B_DATA0 | PIO1_11 | FLEXSPI0B_DATA0 |
| QSPI_B_DATA1 | PIO1_12 | FLEXSPI0B_DATA1 |
| QSPI_B_DATA2 | PIO1_13 | FLEXSPI0B_DATA2 |
| QSPI_B_DATA3 | PIO1_14 | FLEXSPI0B_DATA3 |
| QSPI_B_DATA4 | PIO2_17 | FLEXSPI0B_DATA4 |
| QSPI_B_DATA5 | PIO2_18 | FLEXSPI0B_DATA5 |
| QSPI_B_DATA6 | PIO2_22 | FLEXSPI0B_DATA6 |
| QSPI_B_DATA7 | PIO2_23 | FLEXSPI0B_DATA7 |
| nRESET_QSPI | PIO2_12 | PIO2_12 |
NOTE: The BOOT ROM of the RT600 seems to activate the octa mode under some circumstances. In order to bring the flash into a proper / known state, the J-Link flashloader resets the QSPI flash using the nRESET pin of the flash which is connected to PIO2_12 on the evaluation board.
Example Application
The application toggles 3 LEDs (blue, red and green) on the MIMXRT685-EVK evaluation board. The application is linked into the external flash. It includes a valid boot header so it also runs stand-alone.
SETUP
- J-Link software: V6.62d
- Embedded Studio: V4.50
- Hardware: NXP MIMXRT685-EVK
- Link: File:NXP MIMXRT685-EVK QSPI ES.zip
