NXP i.MXRT600

From SEGGER Wiki
Jump to navigation Jump to search

This article covers the NXP i.MXRT600 MCU family devices.

Tracing on i.MXRT600 series

This section describes how to get started with trace on the NXP i.MXRT600 MCUs. This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). If this is not the case, we recommend to read Trace chapter in the J-Link User Manual (UM08001).

Note:

  • The sample projects come with a pre-configured project file for Ozone that runs out-of-the box.
  • The following sample project is designed to be used with J-Trace PRO for streaming trace and Ozone to demonstrate streaming trace.
  • In order to rebuild the sample project, SEGGER Embedded Studio can be used.
  • The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

Tracing on NXP i.MXRT685S

Minimum requirements

In order to use trace on the NXP i.MXRT685S MCU devices, the following minimum requirements have to be met:

  • J-Link software version V6.80d or later
  • Ozone V3.20b or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO for Cortex-M HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project has been tested with the minimum requirements mentioned above and a NXP MIMXRT685-EVK.

Example project RAM: NXP_iMXRT685_Trace_Example.zip

The RAM trace example should run on any NXP iMXRT685S platform.


Example project QSPI: NXP_IMXRT685_QSPI_TracePins.zip

The QSPI Flash trace sample may only run on boards that use the same components as the mentioned eval board below. You can find the Ozone project file (.jdebug) under the following path in the sample: /Start/BoardSupport/NXP/iMXRT685S_MIMXRT685_EVK

Tested Hardware

NXP MIMXRT685-EVK

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality
Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time

SWO on i.MXRT600 series

The IMXRT600 support 2 different pins for SWO:

Pin function
PIO2_24 FUNC 1
PIO2_31 FUNC 5

For PIO2_24 SWO support is available out-of-the-box for version V6.84 and later. The following SEGGER Embedded Studio Project comes with a compiled J-Link Script file (.pex) used for the initialization of SWO via PIO2_24.

Sample Projects

QSPI Flash

The RT600 does not come with internal flash but with external flash connected to the FlexSPI bus, only. QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for i.MXRT600. The default loader is marked in bold. For details on how to select a specific flash loader, please see here.

Device Bank name Base address Maximum size Supported pin configuration
MIMXRT633S / MIMXRT685S FlexSPI 0x08000000 64 MB
  • Port_B
  • Port_A
MIMXRT633S / MIMXRT685S FlexSPI (secure) 0x18000000 64 MB
  • Port_B
  • Port_A

Port_B

Signal Name GPIO name IO function
QSPI_B_CS0 PIO2_19 FLEXSPI0B_SS0_N
QSPI_B_SCK PIO1_29 FLEXSPI0B_SCLK
QSPI_B_DATA0 PIO1_11 FLEXSPI0B_DATA0
QSPI_B_DATA1 PIO1_12 FLEXSPI0B_DATA1
QSPI_B_DATA2 PIO1_13 FLEXSPI0B_DATA2
QSPI_B_DATA3 PIO1_14 FLEXSPI0B_DATA3
QSPI_B_DATA4 PIO2_17 FLEXSPI0B_DATA4
QSPI_B_DATA5 PIO2_18 FLEXSPI0B_DATA5
QSPI_B_DATA6 PIO2_22 FLEXSPI0B_DATA6
QSPI_B_DATA7 PIO2_23 FLEXSPI0B_DATA7
nRESET_QSPI PIO2_12 PIO2_12

NOTE: The BOOT ROM of the RT600 seems to activate the octa mode under some circumstances. In order to bring the flash into a proper / known state, the J-Link flashloader resets the QSPI flash using the nRESET pin of the flash which is connected to PIO2_12 on the evaluation board.

Port_A

Signal Name GPIO name IO function
QSPI_A_CS0 PIO1_19 FLEXSPI0A_SS0_N
QSPI_A_SCK PIO1_18 FLEXSPI0A_SCLK
QSPI_A_DATA0 PIO1_20 FLEXSPI0A_DATA0
QSPI_A_DATA1 PIO1_21 FLEXSPI0A_DATA1
QSPI_A_DATA2 PIO1_22 FLEXSPI0A_DATA2
QSPI_A_DATA3 PIO1_23 FLEXSPI0A_DATA3
QSPI_A_DATA4 PIO2_24 FLEXSPI0A_DATA4
QSPI_A_DATA5 PIO2_25 FLEXSPI0A_DATA5
QSPI_A_DATA6 PIO2_26 FLEXSPI0A_DATA6
QSPI_A_DATA7 PIO2_27 FLEXSPI0A_DATA7
nRESET_QSPI PIO2_12 PIO2_12

NOTE: The BOOT ROM of the RT600 seems to activate the octa mode under some circumstances. In order to bring the flash into a proper / known state, the J-Link flashloader resets the QSPI flash using the nRESET pin of the flash which is connected to PIO2_12 on the evaluation board.

Example Application

The application toggles 3 LEDs (blue, red and green) on the MIMXRT685-EVK evaluation board. The application is linked into the external flash (connected to FlexSPI port B). It includes a valid boot header so it also runs stand-alone.

SETUP