Difference between revisions of "NXP i.MX 8"
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| − | The '''NXP i.MX 8''' is an embedded multi-core processor consisting of two Cortex-M4, four Cortex-A53 and two Cortex-A72. |
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== Debugging == |
== Debugging == |
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| + | Debugging of Cortex-A72, Cortex-A53 and Cortex-M4 cores is enabled after primary boot stage.<br> |
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| − | J-Link supports debugging for the Cortex-M4. During connect the M4 is set to execute an endless loop at 0x1FFE0000 (TCML RAM) and afterwards halted. |
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| + | A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images packed in containers. |
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| + | After the boot stage J-Link can be attached to a running target. |
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| + | {{Note|After reset a watchdog timer is enabled. System Controller firmware is responsible to pereodicaly refresh the timer. |
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| − | === Reset === |
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| + | }} |
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| − | J-Link currently does not support device reset. |
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Revision as of 12:15, 28 March 2024
Debugging
Debugging of Cortex-A72, Cortex-A53 and Cortex-M4 cores is enabled after primary boot stage.
A boot image should contain System Controller Unit (SCU) and Security Controller (SECO) firmware images packed in containers.
After the boot stage J-Link can be attached to a running target.
Note:
After reset a watchdog timer is enabled. System Controller firmware is responsible to pereodicaly refresh the timer.
