ArteryTek AT32F40x
ArteryTek AT32F40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 1024KB | 
|
| User data | 0x1FFFF800 | up to 512B |
|
| SPIM external flash | 0x08400000 | 16 MB |
|
Notes for use of SPIM external flash
- For the use of SPIM, the user has to take care, when setting up clocks, that AHB clock does not exceed 120 MHz.
- When clocks are not setup, J-Link sets core clock to 200 MHz and AHB clock to 100 MHz during SPIM flash programming.
- Only SPIM Type 2 / EN25QH128A and pin configuration CLK@PB1_CS@PA8_IO0@PB10_IO1@PB11_IO2@PB7_IO3_@PB6 is supported right now.
- SPIM may not be present on all devices of this device family.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F40x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| AT32F402 AT32F405 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
