The HPMicro HPM67xx device series are RISC-V based 32-bit microcontrollers.
SPI flash support
J-Link supports SPI-flashes with HPM67xx through the XPI-API.
Dual Core Debugging
The HPM67 family features two cores. CPU0 is the master CPU and CPU1 is the slave CPU. After reset, CPU0 is enabled while CPU1 is in standby. When necessary, the program image of CPU1 is loaded by CPU0, and then CPU1 is released. The steps are as follows:
- CPU0 writes the code mirror address of CPU1 into the SYSCTL_CPU1_GPR0 register
- CPU0 writes the CPU1 startup code into the SYSCTL_CPU1_GPR1 register, the code is 0xC1BEF1A9
- CPU0 clears the SYSCTL_CPU1_LP [HALT] bit to 0 to release CPU1
The J-Link supports debugging of both cores. The desired CPU can be selected via a dedicated device name such as "HPM6758XXXX" for CPU0 and "HPM6758XXXX_CPU1" for CPU1.
- HPMicro HPM6750EVKMINI: https://wiki.segger.com/HPMicro_HPM6750EVKMINI