J-Link Xtensa specifics

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Debug support

Since V7.70 of the J-Link software, Cadence Xtensa based cores (HiFi 3, HiFi 4, Fusion F1, ...) are supported in the following J-Link utilities:

Note:
For more information which J-Link models come with support for Cadence Xtensa based cores, please refer to the model overview page of the SEGGER website

Debug settings

Most of the Xtensa specific debug settings cannot be auto-detected and must be passed to J-Link via a J-Link script file. The table below lists the settings that need to be provided via the J-Link script file. When licensing a core from Cadence, there is a core config overview provided to the licensee which contains all the information listed below.

Setting Type Meaning Comment
XTENSA_SetNumAddrReg Numeric (decimal) Number of address registers implemented Called "AR registers count" in Cadence core config overview
XTENSA_SetHasCodeDensityOpt Boolean (0 or 1) Indicates if the core implements the density option (16-bit instruction support) ---
XTENSA_SetDebugLevel Numeric (Decimal) Indicates the level of the debug interrupt (Xtensa LX architecture only) Called "Level of debug interrupt" in Cadence core config overview
XTENSA_SetExceptionArch String Indicates the exception architecture used by the core (currently only XEA2 is supported!) ---
XTENSA_SetNumHWInstBP Numeric (Decimal) Indicates the number of instruction hardware breakpoints implemented by the core. Called "Count of HW instruction traps" in Cadence core config overview
XTENSA_SetNumHWDataBP Numeric (Decimal) Indicates the number of data hardware breakpoints implemented by the core. Called "Count of HW data traps" in Cadence core config overview
XTENSA_SetIRAM0 Range (Hexadecimal) Indicates where IRAM0 is located in the address space of the core Needed by J-Link because IRAM0 may only be accessed 32-bit wise.
XTENSA_SetIRAM1 Range (Hexadecimal) Indicates where IRAM1 is located in the address space of the core Needed by J-Link because IRAM1 may only be accessed 32-bit wise.
XTENSA_SetICacheSize Numeric (Hexadecimal) Size of I-cache in bytes Needed by J-Link to perform proper I-cache invalidate after setting/clearing software breakpoints
XTENSA_SetICacheNumWays Numeric (Decimal) Number of ways the I-cache implements Needed by J-Link to perform proper I-cache invalidate after setting/clearing software breakpoints
XTENSA_SetICacheLineSize Numeric (Decimal) Size of a I-cache line in bytes Needed by J-Link to perform proper I-cache invalidate after setting/clearing software breakpoints
XTENSA_SetDCacheSize Numeric (Hexadecimal) Size of D-cache in bytes Needed by J-Link to perform proper D-cache clean & invalidate after setting/clearing software breakpoints
XTENSA_SetDCacheNumWays Numeric (Decimal) Number of ways the D-cache implements Needed by J-Link to perform proper D-cache clean & invalidate after setting/clearing software breakpoints
XTENSA_SetDCacheLineSize Numeric (Decimal) Size of a D-cache line in bytes Needed by J-Link to perform proper D-cache clean & invalidate after setting/clearing software breakpoints
CORESIGHT_SetDebugAPToUse --- Specifies the MEM-AP (AHB-AP, APB-AP) that has access to the core debug registers Needed for DAP based setups only (Xtensa core behind a CoreSight DAP)
JLINK_CORESIGHT_CoreBaseAddr Numeric (Hexadecimal) Specifies the core debug registers base address in the MEM-AP address space Needed for DAP based setups only (Xtensa core behind a CoreSight DAP)


Note:
For more information which hardware version of which J-Link model comes with support for Cadence Xtensa based cores, please refer to the model overview wiki article

Example script file for HiFi 4 KC705 FPGA board bitstream

/***********************************************************************
*                    SEGGER Microcontroller GmbH                       *
*                        The Embedded Experts                          *
************************************************************************
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*                  (c) SEGGER Microcontroller GmbH                     *
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* The use in source and binary forms, with or without modification,    *
* is permitted for internal use only. The redistribution to any        *
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-------------------------- END-OF-HEADER -----------------------------
Purpose: J-Link script file for the Cadence HiFi 4 core bitstream running on the Xilinx KC705 FPGA board.
Literature:
  [1]  N/A

*/

/*********************************************************************
*
*       Constants (similar to defines)
*
**********************************************************************
*/

/*********************************************************************
*
*       Static code
*
**********************************************************************
*/

/*********************************************************************
*
*       Public code
*
**********************************************************************
*/

/*********************************************************************
*
*       ConfigTargetSettings()
*
*  Function description
*    Called before InitTarget(). Mainly used to set some global DLL variables to customize the normal connect procedure.
*    For ARM CoreSight devices this may be specifying the base address of some CoreSight components (ETM, ...)
*    that cannot be automatically detected by J-Link due to erroneous ROM tables etc.
*    May also be used to specify the device name in case debugger does not pass it to the DLL.
*
*  Return value
*    >= 0  O.K.
*     < 0  Error
*
*  Notes
*    (1) May not, under absolutely NO circumstances, call any API functions that perform target communication.
*    (2) Should only set some global DLL variables
*/
int ConfigTargetSettings(void) {
  JLINK_ExecCommand("XTENSA_SetNumAddrReg = 64");         // Called "AR registers count" in Cadence core config overview
  JLINK_ExecCommand("XTENSA_SetHasCodeDensityOpt = 1");
  JLINK_ExecCommand("XTENSA_SetDebugLevel = 6");          // Called "Level of debug interrupt" in Cadence core config overview
  JLINK_ExecCommand("XTENSA_SetExceptionArch = XEA2");
  JLINK_ExecCommand("XTENSA_SetNumHWInstBP = 2");         // Called "Count of HW instruction traps" in Cadence core config overview
  JLINK_ExecCommand("XTENSA_SetNumHWDataBP = 2");         // Called "Count of HW data traps" in Cadence core config overview
  //
  // Tell J-Link about IRAM0 / IRAM1 areas.
  // These are special because only 32-bit accesses are allowed.
  // By design, Cadence XOCD makes accesses to IRAM 32-bit wide (read-modify-write for write accesses < 32-bit).
  // As J-Link should behave compatible, we tell J-Link where these special areas are.
  //
  // For Cadence Xplorer IDE sessions, these execs are usually not needed because Xplorer transmits the regions to J-Link at the start of the debug session.
  // However, it does not hurt to have them in either.
  //
  JLINK_ExecCommand("XTENSA_SetIRAM0 0x3FFE0000, 0x10000");
  JLINK_ExecCommand("XTENSA_SetIRAM1 0x3FFF0000, 0x10000");
  //
  // Cache attributes.
  // Set cache size to 0 (or do not set it at all) in case the core does not implement cache
  //
  JLINK_ExecCommand("XTENSA_SetICacheSize = 0x4000");
  JLINK_ExecCommand("XTENSA_SetICacheNumWays = 4");
  JLINK_ExecCommand("XTENSA_SetICacheLineSize = 32");
  JLINK_ExecCommand("XTENSA_SetDCacheSize = 0x4000");
  JLINK_ExecCommand("XTENSA_SetDCacheNumWays = 4");
  JLINK_ExecCommand("XTENSA_SetDCacheLineSize = 32");
  //
  // DAP based setups only (Xtensa core behind a CoreSight DAP)
  //
  //JLINK_ExecCommand("CORESIGHT_SetDebugAPToUse BaseAddr=0x03000000 Type=AHB-AP");
  //JLINK_CORESIGHT_CoreBaseAddr = 0x0;
  return 0;
}

Cadence Xtensa Xplorer IDE support

Since V7.80 of the J-Link software, JLink GDB Server may be used to replace Cadence XOCD to allow debugging in Cadence Xtensa Xplorer IDE. The native debug support in J-Link GDB Server comes with a great performance boost compared to the low-level PC-based XOCD implementation.

For more information regarding how to setup J-Link GDB Server for Xplorer usage, please refer to the J-Link GDB Server wiki page.

Data breakpoints

  • The data breakpoints for Xtensa do not support break on data comparison, meaning only accesses to certain addresses may halt the core but they always halt the core, no matter what data is written / read. So for all J-Link dialogs etc., the <DataMask> must be 0xFFFFFFFF (all bits do not care).
  • Data breakpoints cannot be configured to trigger to a specific access size only. For example setting a data breakpoint to addr. 0x100 makes it trigger when this address is accessed. No matter if this happens as part of a 8-bit, 16-bit or 32-bit access.
  • The data breakpoints for Xtensa support some kind of address range matching. A data breakpoint can for example configured to monitor accesses to a 1-byte address (e.g. 0x1000) up to a range of 64 bytes (e.g. 0x1000 - 0x103F).

File I/O support

J-Link GDB Server supports the Xtensa Xplorer file I/O operations via the BREAK 14,1 instruction when debugging in Xtensa Xplorer.#

The following file I/O operations are supported:

  • printf()
  • fopen()
  • fprintf()
  • fclose()
  • fread()
  • fseek()
  • rename()
  • fstat()
  • stat()
  • isatty()
  • unlink()
  • gettimeofday()