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Internal option-setting memory

Option-settings memory is located at 0x0100A100 has a size of 512 Bytes.

Internal program flash

The size of the program flash is dependent on the device used.

Device Size (KiB) Memory region
R7FA6M4AD 512 0x00000000 - 0x0007FFFF
R7FA6M4AE 768 0x00000000 - 0x000CFFFF
R7FA6M4AF 1024 0x00000000 - 0x000FFFFF
Currently only single bank flash operations are supported. Dual bank mode is not supported.

Internal data flash

Internal data flash is located at 0x08000000 has a size of 8 KB.

External QSPI flash

External QSPI flash is located at 0x60000000.

Supported pin configurations

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.

  • CLK@P305_nCS@P306_D0@P307_D1@P503_D2@P104_D3@P505 (default)
  • CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505
  • CLK@P305_nCS@P306_D0@P307_D1@P308_D2@P309_D3@P310

Minimum requirements

The Renesas RA6M4 series devices requires special handling for the TrustZone partition registers of the MCU. This requires certain HW support which is not provided by older J-Link models. The following table lists the minimum J-Link HW version needed to support this MCU.

  • J-Link-OB-S124
  • J-Link BASE V10
  • J-Link PLUS V10
  • J-Link ULTRA+ V4
  • J-Link PRO V4
  • J-Link WiFi V1
  • J-Trace PRO V2 Cortex-M
  • J-Trace PRO V2 Cortex

Later versions (e.g. V10 is listed and current HW is V11) will also work.

Note: Models which are not listed here do not support this MCU.

Tracing on RA6M4 series

Tracing on Renesas R7FA6M4

Minimum requirements

In order to use trace on the Renesas R7FA6M4 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.92h or later
  • Ozone V3.30b or later (if streaming trace and / or the sample project from below shall be used)
  • SEGGER Embedded Studio V7.30
  • J-Trace PRO for Cortex-M HW version V2.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project has been tested with the minimum requirements mentioned above and a Renesas EK-RA6M4.

Example project: Renesas_R7FA6M4_TracePins.zip

Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.

To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing

Trace buffer (TMC/ETB)

Theoretically this target devices does implement an ETB for buffer tracing. Unfortunately the chip seems to have a silicon bug so only pin tracing will produce reliable output while buffer tracing does not.

Tested Hardware

Renesas EK-RA6M4 evaluation board

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality
Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time
Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time