Target Interface SWD
ARM's Serial Wire Debug (SWD) replaces the traditional 5-pin JTAG debug interface by introducing a 2-pin interface with a clock (SWDCLK) and a single bi-directional data pin (SWDIO), providing all the normal JTAG debug and test functionality, anyhow dayisy-chaining devices as via JTAG is not possible. SWDIO and SWCLK are overlaid on the TMS and TCK pins, allowing to use the same connector for JTAG and SWD. In order to communicate with a device via SWD, data is send on SWDIO, synchronous to the SWCLK. With every rising edge of SWCLK, one bit of data is transmitted or received on the SWDIO pin.
|Clock signal to target CPU. It is recommended that this pin is pulled to a defined state of the target board. Shared with TMS on targets which support JTAG and SWD.
|Bi-directional data pin. This pin should be pulled up on the target. Shared with TMS on targets which support JTAG and SWD.
|Serial wire output, allowing the CPU to output custom data like printf output, asynchronous to SWCLK and other debug pins. Usually shared with the TDO pin on devices which support JTAG and SWD. Not available on all devices which support SWD.
In addition to the debug signals, ARM's SWD interface also specifies a dedicated pin which allows the target CPU to output specific data like printf output on a dedicates pin via UART or Manchester protocol. This pin is unidirectional, so it is not possible to send data to the target CPU on this pin. Note that not all ARM architectures that support SWD, also support SWO. For more information, please refer to SWO