Difference between revisions of "TI MSPM0G"
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The TI MSPM0G are Cortex-M0 based micro controllers. |
The TI MSPM0G are Cortex-M0 based micro controllers. |
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__TOC__ |
__TOC__ |
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| MAIN || 0x0000_0000 - 0x0020_0000 || {{YES}} || {{YES}} |
| MAIN || 0x0000_0000 - 0x0020_0000 || {{YES}} || {{YES}} |
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|- |
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− | | NONMAIN || 0x41C0_0000 - 0x41C0_0200 || {{YES}} || {{ |
+ | | NONMAIN || 0x41C0_0000 - 0x41C0_0200 || {{YES}} || {{YES}}<ref>See [[#NONMAIN|NONMAIN]]</ref> |
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|- |
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| FACTORY || 0x41C4_0000 - 0x41C4_0080 || {{NO}} || {{NO}} |
| FACTORY || 0x41C4_0000 - 0x41C4_0080 || {{NO}} || {{NO}} |
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|} |
|} |
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+ | <references /> |
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===ECC flash=== |
===ECC flash=== |
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Therefore, blank check via J-Link Software is disabled. |
Therefore, blank check via J-Link Software is disabled. |
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− | == |
+ | === NONMAIN === |
+ | The NONMAIN region is supported by J-Link for programming. |
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+ | However, the NONMAIN holds boot configuration data and therefore must be programmed with extreme care: |
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+ | * Changes of the NONMAIN region take effect after the next hard reset / power cycle. |
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+ | * The device can be locked (non-)permanently by writing NONMAIN. |
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+ | * If the CRC of the BCR and/or BSL blocks are not matching the related data, the device is permanently locked. |
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+ | * Erasing this region will lead to a non-matching CRC, thus locking the device permanently. |
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+ | {{Note|1= |
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+ | #To prevent unintentional locking of the device, J-Link has special handling when programming the NONMAIN region: |
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+ | #* Return an error when the user tries to erase the NONMAIN region. Erase will be done implicitly when programming it. |
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+ | #* Programming will return an error and will neither erase nor program the NONMAIN region in case the user tries to flash data with invalid CRC values. |
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+ | #The user may program program BCR and BSL regions separately. However, this is only possible as long as the [[Read-Modify-Write_Flash | RMW threshold]] is not manually reduced to < 512 bytes by the user (default is 1 KB). |
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+ | }} |
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+ | |||
+ | ==Device Specific Handling== |
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+ | ===Connect=== |
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+ | Some device specific debug bits are set which prevents the device to enter sleep mode / allows debugging of applications which make use of low power modes. |
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+ | === Watchdog === |
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The MSPM0G devices have two windowed watchdogs implemented (WWDG). |
The MSPM0G devices have two windowed watchdogs implemented (WWDG). |
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Apparently, the watchdog counter cannot be read directly. |
Apparently, the watchdog counter cannot be read directly. |
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* Disabled |
* Disabled |
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* Enabled (non-window mode) |
* Enabled (non-window mode) |
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+ | === Reset === |
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− | |||
+ | A device specific reset is performed for this device. |
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− | == Reset == |
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− | + | This is because the peripherals are not reset when executing the [[J-Link_Reset_Strategies#Type_0:_Normal | Cortex-M default reset]]. |
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+ | A SYSRST is executed via the device specific SYSCTL register instead. |
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==Evaluation Boards== |
==Evaluation Boards== |
Latest revision as of 14:37, 15 May 2024
The TI MSPM0G are Cortex-M0 based micro controllers.
Contents
Internal Flash
The internal flash is divided into 3 different regions:
Region name | Range (max) | Programmable | Supported by J-Link |
---|---|---|---|
MAIN | 0x0000_0000 - 0x0020_0000 | ||
NONMAIN | 0x41C0_0000 - 0x41C0_0200 | [1] | |
FACTORY | 0x41C4_0000 - 0x41C4_0080 |
ECC flash
The flash is ECC protected.
- When programming code with J-Link, the device flash controller is set to automatically program the correct ECC values.
- Manual ECC programming is currently not supported by J-Link.
Erased value and Blank Check
- The erased value of the TI MSPM0x devices is non-deterministic. This means that there is no specific erased value for erased flash.
- The device's flash controller will automatically blank check when erasing.
Therefore, blank check via J-Link Software is disabled.
NONMAIN
The NONMAIN region is supported by J-Link for programming. However, the NONMAIN holds boot configuration data and therefore must be programmed with extreme care:
- Changes of the NONMAIN region take effect after the next hard reset / power cycle.
- The device can be locked (non-)permanently by writing NONMAIN.
- If the CRC of the BCR and/or BSL blocks are not matching the related data, the device is permanently locked.
- Erasing this region will lead to a non-matching CRC, thus locking the device permanently.
- To prevent unintentional locking of the device, J-Link has special handling when programming the NONMAIN region:
- Return an error when the user tries to erase the NONMAIN region. Erase will be done implicitly when programming it.
- Programming will return an error and will neither erase nor program the NONMAIN region in case the user tries to flash data with invalid CRC values.
- The user may program program BCR and BSL regions separately. However, this is only possible as long as the RMW threshold is not manually reduced to < 512 bytes by the user (default is 1 KB).
Device Specific Handling
Connect
Some device specific debug bits are set which prevents the device to enter sleep mode / allows debugging of applications which make use of low power modes.
Watchdog
The MSPM0G devices have two windowed watchdogs implemented (WWDG).
Apparently, the watchdog counter cannot be read directly.
For this reason flash programming is only supported for devices where the watchdogs are not running in window mode.
Supported watchdog settings:
- Disabled
- Enabled (non-window mode)
Reset
A device specific reset is performed for this device. This is because the peripherals are not reset when executing the Cortex-M default reset. A SYSRST is executed via the device specific SYSCTL register instead.