Difference between revisions of "Renesas ASSP EASY"
(→Reset) |
|||
(9 intermediate revisions by one other user not shown) | |||
Line 1: | Line 1: | ||
+ | [[Category:Device families]] |
||
The '''Renesas ASSP easy''' are RISC-V based microcontrollers. |
The '''Renesas ASSP easy''' are RISC-V based microcontrollers. |
||
__TOC__ |
__TOC__ |
||
Line 12: | Line 13: | ||
| Config Flash || 0x01010008 || up tp 44 B || style="text-align:center;"| {{YES}} |
| Config Flash || 0x01010008 || up tp 44 B || style="text-align:center;"| {{YES}} |
||
|- |
|- |
||
− | | Data Flash || 0x40100000 || 4 KB || style="text-align:center;"| {{YES}} |
+ | | Data Flash || 0x40100000 || up to 4 KB || style="text-align:center;"| {{YES}} |
|} |
|} |
||
==ECC RAM== |
==ECC RAM== |
||
− | *Device has ECC RAM which has to be initialized before use. |
+ | *Device has ECC RAM which has to be initialized before use. |
− | |||
==Watchdog Handling== |
==Watchdog Handling== |
||
− | *The device |
+ | *The device has 2 watchdogs. |
+ | *Both watchdogs are fed during flash programming. |
||
− | *The device has a watchdog [WATCHDOGNAME]. |
||
− | *The watchdog is fed during flash programming. |
||
− | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
||
− | |||
− | ==Multi-Core Support [OPTIONAL]== |
||
− | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
||
− | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
||
− | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
||
− | Some of the are available with enabled ''lockstep'' mode, only. <br> |
||
− | In below, the debug related multi-core behavior of the J-Link is described for each core: |
||
− | ===Main core=== |
||
− | ====Init/Setup==== |
||
− | *Initializes the ECC RAM, see [[XXX | XXX]] |
||
− | *Enables debugging |
||
− | ====Reset==== |
||
− | *Device specific reset is performed, see [[XXX | XXX]] |
||
− | ====Attach==== |
||
− | *Attach is not supported because the J-Link initializes certain RAM regions by default |
||
− | ===Secondary core(s)=== |
||
− | ====Init/Setup==== |
||
− | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
||
− | *If the secondary core is not enabled yet, it will be enabled / release from reset |
||
− | ====Reset==== |
||
− | No reset is performed. |
||
− | ====Attach==== |
||
− | *Attach is supported / desired |
||
==Device Specific Handling== |
==Device Specific Handling== |
||
===Connect=== |
===Connect=== |
||
+ | *On Connect, the RAM is initialized. |
||
+ | |||
===Reset=== |
===Reset=== |
||
*The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_6 | here]]. |
*The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_6 | here]]. |
||
==Limitations== |
==Limitations== |
||
− | ===Dual Core Support=== |
||
− | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
||
===Attach=== |
===Attach=== |
||
Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
||
− | ===Security=== |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
+ | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
||
− | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
||
==Example Application== |
==Example Application== |
||
+ | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
||
− | *[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]] |
Latest revision as of 13:25, 15 May 2024
The Renesas ASSP easy are RISC-V based microcontrollers.
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Code Flash | 0x00000000 | up to 128 KB | |
Config Flash | 0x01010008 | up tp 44 B | |
Data Flash | 0x40100000 | up to 4 KB |
ECC RAM
- Device has ECC RAM which has to be initialized before use.
Watchdog Handling
- The device has 2 watchdogs.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, the RAM is initialized.
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Limitations
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.