Difference between revisions of "i.MX6SoloX"
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+ | [[Category:Device families]] |
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− | Script files are necessary to connect to the A9 and M4 core. |
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+ | The '''NXP iMX6SoloX''' are multi-core MCUs composed of a Cortex-M4 and Cortex-A9 core. |
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+ | __TOC__ |
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+ | ==Flash Banks== |
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− | How to use J-Link script files: |
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+ | ===QSPI Flash=== |
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− | Please refer to J-Link User Guide (UM08001), chapter 5.10 "J-Link script files" |
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+ | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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+ | J-Link supports the following pin configurations for iMX6SoloX: |
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+ | {| class="seggertable" |
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− | Startup procedure is: |
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+ | |- |
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− | 1) Start debug session that connects to A9 and let it run the application to the point that enables the M4 |
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+ | ! Alternate function !! Port / Pin |
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− | 2) Start debug session that connects to M4 |
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+ | |- |
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− | [...] |
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+ | | QSPI2A_SS0_B || IOMUXC_SW_MUX_CTL_PAD_NAND_ALE |
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− | x) Close debug session that connects to M4 |
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+ | |- |
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− | x + 1) Close debug session that connects to A9 |
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+ | | QSPI2A_DATA2 || IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B |
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+ | |- |
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+ | | QSPI2A_DATA3 || IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B |
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+ | |- |
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+ | | QSPI2A_SCLK || IOMUXC_SW_MUX_CTL_PAD_NAND_CLE |
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+ | |- |
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+ | | QSPI2A_DATA1 || IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B |
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+ | |- |
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+ | | QSPI2A_DATA0 || IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B |
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+ | |} |
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+ | ==Multi-Core Support == |
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+ | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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+ | The iMX6SoloX family feature a Cortex-A9 and Cortex-M4 core.<br> |
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+ | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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+ | ===Cortex-A9=== |
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+ | ====Init/Setup==== |
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+ | *Enables debugging |
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+ | ====Reset==== |
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+ | *No Reset is performed. |
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+ | ===Secondary core(s)=== |
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+ | ====Init/Setup==== |
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+ | *Enables debugging |
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+ | ====Reset==== |
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+ | *No reset is performed. |
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+ | ==Evaluation Boards== |
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− | '''Important!''' |
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+ | *[[NXP iMX6SX SABRE]] |
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− | On the SoloX the M4 cannot be independently debugged without having something running on the A9 that enables the M4. |
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+ | |||
− | Since Freescale removed some features from the i.MX6 to the SoloX, it is no longer possible to easily enable the M4 from the debug interface and so being able to debug it completely independent from the A9. |
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+ | ==Example Application== |
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+ | *[[NXP iMX6SX SABRE#Example_Project | NXP iMX6SX SABRE]] |
Latest revision as of 13:06, 15 May 2024
The NXP iMX6SoloX are multi-core MCUs composed of a Cortex-M4 and Cortex-A9 core.
Contents
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports the following pin configurations for iMX6SoloX:
Alternate function | Port / Pin |
---|---|
QSPI2A_SS0_B | IOMUXC_SW_MUX_CTL_PAD_NAND_ALE |
QSPI2A_DATA2 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B |
QSPI2A_DATA3 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B |
QSPI2A_SCLK | IOMUXC_SW_MUX_CTL_PAD_NAND_CLE |
QSPI2A_DATA1 | IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B |
QSPI2A_DATA0 | IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B |
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX6SoloX family feature a Cortex-A9 and Cortex-M4 core.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A9
Init/Setup
- Enables debugging
Reset
- No Reset is performed.
Secondary core(s)
Init/Setup
- Enables debugging
Reset
- No reset is performed.