Difference between revisions of "ONSemi RSL10"
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==Reset== |
==Reset== |
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− | It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which |
+ | It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which makes sure that CPU is halted right before the target application but after boot ROM. |
==Evaluation Boards== |
==Evaluation Boards== |
Revision as of 18:51, 10 December 2020
The RSL10 family from ON Semiconductor is an ultra-low-power SoC designed for use in high−performance applications focused on wearable and medical applications. The SoC features a Cortex-M3 core and supports bluetooth low energy technology and any 2.4 GHz proprietary protocol stacks, without sacrificing power consumption.
On-Chip Memory Regions
The internal flash is divided into 5 different regions:
Instance Name | Size (bytes) | Memory region |
---|---|---|
Main Flash | 393216 | 0x00100000 - 0x0015FFFF |
Non-Volatile Record (NVR) 1 | 2048 | 0x00080000 - 0x000807FF |
Non-Volatile Record (NVR) 2 | 2048 | 0x00080800 - 0x00080FFF |
Non-Volatile Record (NVR) 3 | 2048 | 0x00081000 - 0x000807FF |
Non-Volatile Record (NVR) 4 (Manufacturing Test) |
1024 | 0x00081800 - 0x00080BFF |
NOTE: J-Link supports the Main Flash as well as NVR1 - NVR3.
Reset
It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which makes sure that CPU is halted right before the target application but after boot ROM.
Evaluation Boards
- ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP
Example Application
- ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP#Example_Project