Difference between revisions of "ArteryTek AT32F40x"
| Line 32: | Line 32: | ||
==Evaluation Boards== |
==Evaluation Boards== |
||
| + | *[[Artery_AT-START-F402|Artery AT-START-F402]] |
||
*[[Artery_AT-START-F405|Artery AT-START-F405]] |
*[[Artery_AT-START-F405|Artery AT-START-F405]] |
||
==Example Application== |
==Example Application== |
||
| + | *[[Artery_AT-START-F402#Example_Project | Artery AT-START-F402]] |
||
*[[Artery_AT-START-F405#Example_Project | Artery AT-START-F405]] |
*[[Artery_AT-START-F405#Example_Project | Artery AT-START-F405]] |
||
Revision as of 14:22, 25 January 2024
Artery AT32F40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256KB | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| AT32F402 AT32F405 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
