Difference between revisions of "ArteryTek AT32F40x"
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===QSPI Flash=== |
===QSPI Flash=== |
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QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for |
+ | J-Link supports multiple pin configurations for AT32F40x. The default loader is marked in '''bold'''. |
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Revision as of 18:22, 7 February 2024
Artery AT32F40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256KB | 
|
| SPIM external flash | 0x08400000 | Up to 16 MB | 
|
The SPIM support is currently under development.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F40x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| AT32F402 AT32F405 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
