Difference between revisions of "ArteryTek AT32F40x"
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | Internal flash || 0x08000000 || Up to |
+ | | Internal flash || 0x08000000 || Up to 256KB || style="text-align:center;"| {{YES}} |
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! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
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| − | | |
+ | | AT32F402<br> |
| + | AT32F405 |
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| − | AT32F435<br> |
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| − | AT32F437 |
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|| 0x90000000 || Up to 64 MB || |
|| 0x90000000 || Up to 64 MB || |
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| − | *'''CLK@ |
+ | *'''CLK@PB2_CS@PC11_IO0@PC9_IO1@PB7_IO2@PC8_IO3_@CP5''' |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[Artery_AT-START- |
+ | *[[Artery_AT-START-F405|Artery AT-START-F405]] |
| − | *[[Artery_AT-START-F437|Artery AT-START-F437]] |
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==Example Application== |
==Example Application== |
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| − | *[[Artery_AT-START- |
+ | *[[Artery_AT-START-F405#Example_Project | Artery AT-START-F405]] |
| − | *[[Artery_AT-START-F437#Example_Project | Artery AT-START-F437]] |
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Revision as of 12:21, 25 January 2024
Artery AT32F40x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 256KB | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| AT32F402 AT32F405 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
