ArteryTek AT32F40x

Artery AT32F40x are Cortex-M4 based MCUs

Flash Banks

Internal Flash

Flash Bank	Base address	Size	J-Link Support
Internal flash	0x08000000	Up to 1024KB
SPIM external flash	0x08400000	Up to 16 MB

The SPIM support is currently under development.

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F40x. The default loader is marked in bold.

Device	Base address	Maximum size	Supported pin configuration
AT32F402 AT32F405	0x90000000	Up to 64 MB	CLK@PB2_CS@PC11_IO0@PC9_IO1@PB7_IO2@PC8_IO3_@CP5

Watchdog Handling

• The watchdog is fed during flash programming.

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

• Artery AT-START-F402
• Artery AT-START-F403A
• Artery AT-START-F405
• Artery AT-START-F407

Example Application

• Artery AT-START-F402
• Artery AT-START-F403A
• Artery AT-START-F405
• Artery AT-START-F407