Difference between revisions of "ArteryTek AT32F43x"
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==Evaluation Boards== |
==Evaluation Boards== |
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*Artery AT-START-F435 evaluation board: https://wiki.segger.com/Artery_AT-START_F435 |
*Artery AT-START-F435 evaluation board: https://wiki.segger.com/Artery_AT-START_F435 |
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+ | |||
+ | |||
+ | The '''[SiliconVendor] [DeviceFamily]''' are [SHORT_DESCRIPTION] |
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+ | __TOC__ |
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+ | |||
+ | ==Flash Banks== |
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+ | ===Internal Flash=== |
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+ | {| class="seggertable" |
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+ | |- |
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+ | ! Flash Bank || Base address !! Size || J-Link Support |
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+ | |- |
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+ | | [BANK_NAME] || [BANK_BASE_ADDRESS] || Up to [FLASH_SIZE] KB || style="text-align:center;"| {{YES}} / {{NO}} |
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+ | |} |
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+ | |||
+ | ====ECC Flash [OPTIONAL]==== |
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+ | *Describe ECC Flash restriction here. |
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+ | |||
+ | ===QSPI Flash=== |
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+ | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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+ | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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+ | {| class="seggertable" |
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+ | |- |
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+ | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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+ | |- |
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+ | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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+ | *'''[LOADER_NAME]''' |
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+ | *[LOADER_NAME] |
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+ | *[LOADER_NAME] |
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+ | |} |
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+ | |||
+ | ==ECC RAM [OPTIONAL]== |
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+ | *Describe ECC RAM restriction here. |
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+ | |||
+ | ==Vector Table Remap [OPTIONAL]== |
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+ | *Describe Vector Table Remap here.. |
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+ | |||
+ | ==Watchdog Handling== |
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+ | *The device does not have a watchdog. |
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+ | *The device has a watchdog [WATCHDOGNAME]. |
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+ | *The watchdog is fed during flash programming. |
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+ | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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+ | |||
+ | ==Multi-Core Support [OPTIONAL]== |
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+ | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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+ | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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+ | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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+ | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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+ | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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+ | ===Main core=== |
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+ | ====Init/Setup==== |
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+ | *Initializes the ECC RAM, see [[XXX | XXX]] |
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+ | *Enables debugging |
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+ | ====Reset==== |
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+ | *Device specific reset is performed, see [[XXX | XXX]] |
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+ | ====Attach==== |
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+ | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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+ | ===Secondary core(s)=== |
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+ | ====Init/Setup==== |
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+ | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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+ | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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+ | ====Reset==== |
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+ | No reset is performed. |
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+ | ====Attach==== |
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+ | *Attach is supported / desired |
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+ | |||
+ | ==Device Specific Handling== |
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+ | ===Connect=== |
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+ | ===Reset=== |
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+ | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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+ | *The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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+ | *The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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+ | *The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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+ | *The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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+ | *The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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+ | *The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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+ | *The device uses custom reset:..... |
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+ | |||
+ | ==Limitations== |
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+ | ===Dual Core Support=== |
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+ | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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+ | ===Attach=== |
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+ | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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+ | ===Security=== |
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+ | |||
+ | ==Evaluation Boards== |
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+ | *[[Artery_AT-START-F435|Artery AT-START-F435]] |
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+ | |||
+ | ==Example Application== |
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+ | *[[Artery_AT-START-F435#Example_Project | Artery AT-START-F435]] |
Revision as of 14:42, 18 January 2024
Contents
The Artery AT32F43x are Cortex-M4 based MCUs.
Internal Flash
Supported Regions
The internal flash is divided into 3 different regions:
- Main storage area starting at 0x08000000 with up to 4032KB
- Reserved bootloader area starting at 0x1FFF0000 with 16KB
- User system data starting at 0x1FFFC000 with 4KB
For now, the J-Link supports the main storage from V7.88l.
Reset
No device specific reset is necessary. The normal Cortex-M reset is performed.
See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Type_0:_Normal
Evaluation Boards
- Artery AT-START-F435 evaluation board: https://wiki.segger.com/Artery_AT-START_F435
The [SiliconVendor] [DeviceFamily] are [SHORT_DESCRIPTION]
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
[BANK_NAME] | [BANK_BASE_ADDRESS] | Up to [FLASH_SIZE] KB | / |
ECC Flash [OPTIONAL]
- Describe ECC Flash restriction here.
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
[DEVICE] | [BANK_BASE_ADDRESS] | [MAX_SPI_FLASH_SIZE] MB |
|
ECC RAM [OPTIONAL]
- Describe ECC RAM restriction here.
Vector Table Remap [OPTIONAL]
- Describe Vector Table Remap here..
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
- The device uses Cortex-M Core reset, no special handling necessary, like described here.
- The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses Cortex-A reset, no special handling necessary, like described here.
- The device uses Cortex-R reset, no special handling necessary, like described here.
- The device uses ARMv8-A reset, no special handling necessary, like described here.
- The device uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.