Difference between revisions of "ArteryTek AT32F43x"
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− | __TOC__ |
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− | The Artery AT32F43x are Cortex-M4 based MCUs. |
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− | ==Internal Flash== |
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− | ===Supported Regions=== |
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− | The internal flash is divided into 3 different regions: |
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− | *Main storage area starting at 0x08000000 with up to 4032KB |
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− | *Reserved bootloader area starting at 0x1FFF0000 with 16KB |
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− | *User system data starting at 0x1FFFC000 with 4KB |
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− | For now, the J-Link supports the main storage from V7.88l. |
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− | ==Reset== |
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− | No device specific reset is necessary. The normal Cortex-M reset is performed. |
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− | See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Type_0:_Normal |
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− | https://wiki.segger.com/Artery_AT-START_F435 |
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− | |||
Artery AT32F43x are Cortex-M4 based MCUs |
Artery AT32F43x are Cortex-M4 based MCUs |
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__TOC__ |
__TOC__ |
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− | ====ECC Flash [OPTIONAL]==== |
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− | *Describe ECC Flash restriction here. |
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===QSPI Flash=== |
===QSPI Flash=== |
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! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
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+ | | AT32F435 |
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− | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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+ | AT32F435 |
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− | *'''[LOADER_NAME]''' |
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+ | || 0x90000000 || Up to 64 MB || |
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− | *[LOADER_NAME] |
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+ | *'''CLK@PF10_CS@PG6_IO@PF9_IO1@PF8_IO2@PF7_IO3_@PF6''' |
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− | *[LOADER_NAME] |
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Revision as of 14:49, 18 January 2024
Artery AT32F43x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal flash | 0x08000000 | Up to 4096 KB | |
QSPI1 flash | 0x90000000 | Up to 64 MB | |
QSPI2 flash | 0xB0000000 | Up to 64 MB |
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
AT32F435
AT32F435 |
0x90000000 | Up to 64 MB |
|
ECC RAM [OPTIONAL]
- Describe ECC RAM restriction here.
Vector Table Remap [OPTIONAL]
- Describe Vector Table Remap here..
Watchdog Handling
- The device does not have a watchdog.
- The device has a watchdog [WATCHDOGNAME].
- The watchdog is fed during flash programming.
- If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards.
Multi-Core Support [OPTIONAL]
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The [DeviceFamily]family comes with a variety of multi-core options.
Some devices from this family feature a secondary core which is disabled after reset / by default.
Some of the are available with enabled lockstep mode, only.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Main core
Init/Setup
- Initializes the ECC RAM, see XXX
- Enables debugging
Reset
- Device specific reset is performed, see XXX
Attach
- Attach is not supported because the J-Link initializes certain RAM regions by default
Secondary core(s)
Init/Setup
- If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
- If the secondary core is not enabled yet, it will be enabled / release from reset
Reset
No reset is performed.
Attach
- Attach is supported / desired
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
- The device uses Cortex-M Core reset, no special handling necessary, like described here.
- The device uses Cortex-M Rest Pin, no special handling necessary, like described here.
- The device uses Cortex-A reset, no special handling necessary, like described here.
- The device uses Cortex-R reset, no special handling necessary, like described here.
- The device uses ARMv8-A reset, no special handling necessary, like described here.
- The device uses ARMv8-R reset, no special handling necessary, like described here.
- The device uses custom reset:.....
Limitations
Dual Core Support
Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.