Difference between revisions of "ArteryTek AT32F43x"
(→QSPI Flash) |
|||
| Line 28: | Line 28: | ||
*'''CLK@PF10_CS@PG6_IO@PF9_IO1@PF8_IO2@PF7_IO3_@PF6''' |
*'''CLK@PF10_CS@PG6_IO@PF9_IO1@PF8_IO2@PF7_IO3_@PF6''' |
||
|} |
|} |
||
| − | |||
| − | ==ECC RAM [OPTIONAL]== |
||
| − | *Describe ECC RAM restriction here. |
||
| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
||
| − | *Describe Vector Table Remap here.. |
||
==Watchdog Handling== |
==Watchdog Handling== |
||
| − | *The device does not have a watchdog. |
||
| − | *The device has a watchdog [WATCHDOGNAME]. |
||
*The watchdog is fed during flash programming. |
*The watchdog is fed during flash programming. |
||
| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
||
| − | |||
| − | ==Multi-Core Support [OPTIONAL]== |
||
| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
||
| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
||
| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
||
| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
||
| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
||
| − | ===Main core=== |
||
| − | ====Init/Setup==== |
||
| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
||
| − | *Enables debugging |
||
| − | ====Reset==== |
||
| − | *Device specific reset is performed, see [[XXX | XXX]] |
||
| − | ====Attach==== |
||
| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
||
| − | ===Secondary core(s)=== |
||
| − | ====Init/Setup==== |
||
| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
||
| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
||
| − | ====Reset==== |
||
| − | No reset is performed. |
||
| − | ====Attach==== |
||
| − | *Attach is supported / desired |
||
==Device Specific Handling== |
==Device Specific Handling== |
||
| Line 68: | Line 36: | ||
===Reset=== |
===Reset=== |
||
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
||
| − | *The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
||
| − | *The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
||
| − | *The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
||
| − | *The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
||
| − | *The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
||
| − | *The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
||
| − | *The device uses custom reset:..... |
||
| − | ==Limitations== |
||
| − | ===Dual Core Support=== |
||
| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
||
| − | ===Attach=== |
||
| − | Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
||
| − | ===Security=== |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
Revision as of 14:50, 18 January 2024
Artery AT32F43x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 4096 KB | 
|
| QSPI1 flash | 0x90000000 | Up to 64 MB |
|
| QSPI2 flash | 0xB0000000 | Up to 64 MB | 
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| AT32F435
AT32F435 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
