Difference between revisions of "ArteryTek AT32F43x"
Arne.kulinna (talk | contribs) (Created page with "__TOC__ The Artery AT32F43x are Cortex-M4 based MCUs. ==Internal Flash== ===Supported Regions=== The internal flash is divided into 3 different regions: *Main storage area s...") |
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| + | ArteryTek AT32F43x are Cortex-M4 based MCUs |
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__TOC__ |
__TOC__ |
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| − | The Artery AT32F43x are Cortex-M4 based MCUs. |
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| − | == |
+ | ==Flash Banks== |
| − | === |
+ | ===Internal Flash=== |
| + | {| class="seggertable" |
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| + | |- |
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| + | ! Flash Bank || Base address !! Size || J-Link Support |
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| + | |- |
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| + | | Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | User data || 0x1FFFC000 || 4 KB || style="text-align:center;"| {{YES}} |
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| + | |} |
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| + | ===QSPI Flash=== |
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| − | The internal flash is divided into 3 different regions: |
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| + | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | *Main storage area starting at 0x08000000 with up to 4032KB |
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| + | J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in '''bold'''. |
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| − | *Reserved bootloader area starting at 0x1FFF0000 with 16KB |
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| + | {| class="seggertable" |
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| − | *User system data starting at 0x1FFFC000 with 4KB |
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| + | |- |
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| − | For now, the J-Link supports the main storage. |
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| + | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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| + | |- |
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| + | | '''QSPI1'''<br> |
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| + | AT32F435<br> |
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| + | AT32F437 |
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| + | || 0x90000000 || Up to 64 MB || |
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| + | *'''CLK@PF10 CS@PG6 IO0@PF9 IO1@PF8 IO2@PF7 IO3_@PF6''' |
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| + | |} |
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| + | ==Watchdog Handling== |
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| − | ==Reset== |
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| + | *The watchdog is fed during flash programming. |
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| − | No device specific reset is necessary. The normal Cortex-M reset is performed. |
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| + | ==Device Specific Handling== |
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| − | See here for more information: https://wiki.segger.com/J-Link_Reset_Strategies#Type_0:_Normal |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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| + | |||
| + | ===Reset=== |
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| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| + | |||
| + | ==Evaluation Boards== |
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| + | *[[ArteryTek_AT-START-F435|ArteryTek AT-START-F435]] |
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| + | *[[ArteryTek_AT-START-F437|ArteryTek AT-START-F437]] |
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| + | |||
| + | ==Example Application== |
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| + | *[[ArteryTek_AT-START-F435#Example_Project | ArteryTek AT-START-F435]] |
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| + | *[[ArteryTek_AT-START-F437#Example_Project | ArteryTek AT-START-F437]] |
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Latest revision as of 13:00, 18 March 2024
ArteryTek AT32F43x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 4096 KB | 
|
| User data | 0x1FFFC000 | 4 KB |
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| QSPI1 AT32F435 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
