Difference between revisions of "ArteryTek AT32F43x"
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| − | + | ArteryTek AT32F43x are Cortex-M4 based MCUs |
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| Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}} |
| Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | User data || 0x1FFFC000 || 4 KB || style="text-align:center;"| {{YES}} |
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! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
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| − | | QSPI1 |
+ | | '''QSPI1'''<br> |
| − | AT32F435 |
+ | AT32F435<br> |
| + | AT32F437 |
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| − | AT32F435 |
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|| 0x90000000 || Up to 64 MB || |
|| 0x90000000 || Up to 64 MB || |
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| − | *'''CLK@ |
+ | *'''CLK@PF10 CS@PG6 IO0@PF9 IO1@PF8 IO2@PF7 IO3_@PF6''' |
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==Device Specific Handling== |
==Device Specific Handling== |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
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| + | |||
===Reset=== |
===Reset=== |
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*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F435|ArteryTek AT-START-F435]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F437|ArteryTek AT-START-F437]] |
==Example Application== |
==Example Application== |
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| − | *[[ |
+ | *[[ArteryTek_AT-START-F435#Example_Project | ArteryTek AT-START-F435]] |
| − | *[[ |
+ | *[[ArteryTek_AT-START-F437#Example_Project | ArteryTek AT-START-F437]] |
Latest revision as of 13:00, 18 March 2024
ArteryTek AT32F43x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Internal flash | 0x08000000 | Up to 4096 KB | 
|
| User data | 0x1FFFC000 | 4 KB |
|
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
| Device | Base address | Maximum size | Supported pin configuration |
|---|---|---|---|
| QSPI1 AT32F435 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
