Difference between revisions of "ArteryTek AT32F43x"
(→QSPI Flash) |
(→Internal Flash) |
||
(6 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
− | + | ArteryTek AT32F43x are Cortex-M4 based MCUs |
|
__TOC__ |
__TOC__ |
||
Line 9: | Line 9: | ||
|- |
|- |
||
| Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}} |
| Internal flash || 0x08000000 || Up to 4096 KB || style="text-align:center;"| {{YES}} |
||
+ | |- |
||
+ | | User data || 0x1FFFC000 || 4 KB || style="text-align:center;"| {{YES}} |
||
|} |
|} |
||
Line 18: | Line 20: | ||
! Device !! Base address !! Maximum size !! Supported pin configuration |
! Device !! Base address !! Maximum size !! Supported pin configuration |
||
|- |
|- |
||
− | | '''QSPI1''' |
+ | | '''QSPI1'''<br> |
− | AT32F435 |
+ | AT32F435<br> |
+ | AT32F437 |
||
− | AT32F435 |
||
|| 0x90000000 || Up to 64 MB || |
|| 0x90000000 || Up to 64 MB || |
||
− | *'''CLK@ |
+ | *'''CLK@PF10 CS@PG6 IO0@PF9 IO1@PF8 IO2@PF7 IO3_@PF6''' |
|} |
|} |
||
Line 29: | Line 31: | ||
==Device Specific Handling== |
==Device Specific Handling== |
||
+ | ===Connect=== |
||
+ | *On Connect, protection level is checked. For further information regarding this, please click [[ArteryTek_AT32| here]]. |
||
+ | |||
===Reset=== |
===Reset=== |
||
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
*The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
||
==Evaluation Boards== |
==Evaluation Boards== |
||
− | *[[ |
+ | *[[ArteryTek_AT-START-F435|ArteryTek AT-START-F435]] |
− | *[[ |
+ | *[[ArteryTek_AT-START-F437|ArteryTek AT-START-F437]] |
==Example Application== |
==Example Application== |
||
− | *[[ |
+ | *[[ArteryTek_AT-START-F435#Example_Project | ArteryTek AT-START-F435]] |
− | *[[ |
+ | *[[ArteryTek_AT-START-F437#Example_Project | ArteryTek AT-START-F437]] |
Latest revision as of 13:00, 18 March 2024
ArteryTek AT32F43x are Cortex-M4 based MCUs
Contents
Flash Banks
Internal Flash
Flash Bank | Base address | Size | J-Link Support |
---|---|---|---|
Internal flash | 0x08000000 | Up to 4096 KB | |
User data | 0x1FFFC000 | 4 KB |
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.
Device | Base address | Maximum size | Supported pin configuration |
---|---|---|---|
QSPI1 AT32F435 |
0x90000000 | Up to 64 MB |
|
Watchdog Handling
- The watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.