ArteryTek AT32F43x

Artery AT32F43x are Cortex-M4 based MCUs

Flash Banks

Internal Flash

Flash Bank	Base address	Size	J-Link Support
Internal flash	0x08000000	Up to 4096 KB

QSPI Flash

QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports multiple pin configurations for AT32F43x. The default loader is marked in bold.

Device	Base address	Maximum size	Supported pin configuration
QSPI1 AT32F435 AT32F435	0x90000000	Up to 64 MB	CLK@PF10_CS@PG6_IO@PF9_IO1@PF8_IO2@PF7_IO3_@PF6

Watchdog Handling

• The watchdog is fed during flash programming.

Device Specific Handling

Reset

• The device uses normal Cortex-M reset, no special handling necessary, like described here.

Evaluation Boards

• Artery AT-START-F435
• Artery AT-START-F437

Example Application

• Artery AT-START-F435
• Artery AT-START-F437