Difference between revisions of "GigaDevice GD32E5"
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The GigaDevice GD32E5 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor. The GD32E5 devices belong to the high performance line of GigaDevices GD32 MCU series. |
The GigaDevice GD32E5 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor. The GD32E5 devices belong to the high performance line of GigaDevices GD32 MCU series. |
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| + | __TOC__ |
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| − | ==On-Chip Memory Regions== |
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| + | |||
| − | The internal flash is divided into 4 different regions:<br> |
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| + | ==Flash Banks== |
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| − | *Main Flash Block (0x08000000 - 0x0807FFFF) |
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| + | ===Internal Flash=== |
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| − | *Information Block (GD32E50x_HD: 0x1FFFF000 - 0x1FFFF7FF; GD32E50x_CL: 0x1FFFB000 - 0x1FFFF7FF) |
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| + | {| class="seggertable" |
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| − | *Option bytes Block (0x1FFFF800 - 0x1FFFF80F) |
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| + | |- |
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| − | *One-time program Block (0x1FFF7000 - 0x1FFF77FF) |
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| + | ! Flash Bank || Base address !! Size || J-Link Support |
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| + | |- |
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| + | | Main flash || 0x08000000 || Up to 64 KB || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | Option Bytes || 0x1FFFF800 || 16 B || style="text-align:center;"| {{YES}} |
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| + | |- |
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| + | | OTP Bytes || 0x1FFF7000 || 512 B || style="text-align:center;"| {{NO}} |
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| + | |} |
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| + | |||
| + | ==Watchdog Handling== |
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| + | *The device does have 2 watchdogs, FWDGT and WWDGT. |
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| + | *The WWDGT watchdog is fed during flash programming. |
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| + | |||
| + | ==Device Specific Handling== |
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| + | ===Connect=== |
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| + | *On Connect, protection level is checked. For further information regarding this, please click [[GigaDevice_GD32| here]]. |
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| + | ===Reset=== |
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| − | For now, the Main Flash Block is supported, only. |
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| + | *The device uses normal Cortex-M reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal | here]]. |
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| − | ==Reset== |
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| − | No special reset is required. |
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==Evaluation Boards== |
==Evaluation Boards== |
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| − | *GigaDevice GD32E503R- |
+ | *[[GigaDevice_GD32E503R-START | GigaDevice GD32E503R-STAR ]] |
| + | *[[GigaDevice_GD32E507Z-EVAL| GigaDevice GD32E507Z-EVAL]] |
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| − | *GigaDevice GD32E507Z-EVAL: https://wiki.segger.com/GigaDevice_GD32E507Z-EVAL |
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==Example Application== |
==Example Application== |
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| − | * |
+ | *[[GigaDevice_GD32E503R-START#Example_Project | GigaDevice GD32E503R-STAR ]] |
| + | *[[GigaDevice_GD32E507Z-EVAL#Example_Project | GigaDevice GD32E507Z-EVAL]] |
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| − | *GigaDevice GD32E507Z-EVAL: https://wiki.segger.com/GigaDevice_GD32E507Z-EVAL#Example_Project |
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Revision as of 11:12, 1 March 2024
The GigaDevice GD32E5 series are 32-bit general-purpose microcontrollers based on the ARM Cortex-M4 processor. The GD32E5 devices belong to the high performance line of GigaDevices GD32 MCU series.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Main flash | 0x08000000 | Up to 64 KB | 
|
| Option Bytes | 0x1FFFF800 | 16 B |
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| OTP Bytes | 0x1FFF7000 | 512 B | 
|
Watchdog Handling
- The device does have 2 watchdogs, FWDGT and WWDGT.
- The WWDGT watchdog is fed during flash programming.
Device Specific Handling
Connect
- On Connect, protection level is checked. For further information regarding this, please click here.
Reset
- The device uses normal Cortex-M reset, no special handling necessary, like described here.
