Difference between revisions of "Infineon CYT2B6"
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| Work flash small area || 0x1400C000 || 0x1400FFFF || 128 B || 128 || 16 KiB |
| Work flash small area || 0x1400C000 || 0x1400FFFF || 128 B || 128 || 16 KiB |
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+ | |||
+ | ==Example Application== |
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+ | The following example projects were created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU inside. It is a simple Hello World sample linked into the internal flash. |
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+ | |||
+ | '''SETUP''' |
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+ | *J-Link software: V7.52ba |
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+ | *Embedded Studio: V5.50d |
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+ | *Hardware: CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU |
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+ | *Link: [[File:Cypress_CYT2B65BAD_M0.zip]] |
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+ | *Link: [[File:Cypress_CYT2B65BAD_M4.zip]] |
Revision as of 16:09, 10 August 2021
CYT2B6 (TVII-B-E-512K) is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
Flash memory layout
The CYT2B6 series devices have 576 KiB Code flash and a 64 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
Flash | Start adress | End adress | Sector size | Sector count | Total size |
---|---|---|---|---|---|
Code flash large area | 0x10000000 | 0x1006FFFF | 32 KiB | 14 | 448 KiB |
Code flash small area | 0x10070000 | 0x1008FFFF | 8 KiB | 16 | 128 KiB |
Work flash large area | 0x14000000 | 0x1400BFFF | 2 KiB | 24 | 48 KiB |
Work flash small area | 0x1400C000 | 0x1400FFFF | 128 B | 128 | 16 KiB |
Example Application
The following example projects were created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU inside. It is a simple Hello World sample linked into the internal flash.
SETUP
- J-Link software: V7.52ba
- Embedded Studio: V5.50d
- Hardware: CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU
- Link: File:Cypress CYT2B65BAD M0.zip
- Link: File:Cypress CYT2B65BAD M4.zip