NXP S32K3xx

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The S32K3 family from NXP includes Cortex-M7 based MCUs in single or dual core configurations supporting ASIL B/D safety applications. The S32K3 family is supported since J-Link software version V6.89c.
NOTE: There are different device configurations available. For details regarding which configurations are available and which are supported by the J-Link software, please get in touch with NXP (NDA required). Due to the fact that most device information are under NDA, SEGGER is allowed to provide very limited support, only. If you encounter any issues with the S32K3 device support, we recommend to get in touch with NXP directly. They will involve us if required.

Internal Flash

Supported Regions

Following flash regions are supported by the J-Link:

  • Code flash memory 0 (0x00400000 - 0x004FFFFF)
  • Code flash memory 1 (0x00500000 - 0x005FFFFF)
  • Code flash memory 2 (0x00600000 - 0x006FFFFF)
  • Code flash memory 3 (0x00700000 - 0x007F3FFF)
  • Data flash memory (0x10000000 - 0x1003FFFF)

RAM

The ITCM and DTCM must be properly initialized with correct ECC before any read operation to avoid any code runaway or software malfucntion or core lockup. ITCM must be initialized with 64-bit writes whereas DTCM can be initialized with 32-bit or 64-bit writes. The J-Link initializes the entire DTCM RAM on connect / after reset. The ITCM is not initialized but needs to be initialized by the application code.

Reset

The J-Link performs a device specific reset sequence.
NOTE: The reset pin needs to be connected in order to guarantee a proper reset.

Limitations

Some S32K3 devices features a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions.

Evaluation Boards

Example Application

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