NXP S32K3xx

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The S32K3 family from NXP includes Cortex-M7 based MCUs in single or dual core configurations supporting ASIL B/D safety applications. The S32K3 family is supported since J-Link software version V6.89c.

Internal Flash

Supported Regions

S32K311

Flash Bank Base address Size J-Link Support
Code flash 0 0x00400000 Up to 512 KB YES.png
Code flash 1 0x00480000 Up to 512 KB YES.png
Data flash 0x10000000 Up to 64 KB YES.png
UTEST 0x1B000000 Up to 8 KB NO.png

S32K312, S32K322 and S32K342

Flash Bank Base address Size J-Link Support
Code flash 0 0x00400000 Up to 1 MB YES.png
Code flash 1 0x00500000 Up to 1 MB YES.png
Data flash 0x10000000 Up to 128 KB YES.png
UTEST 0x1B000000 Up to 8 KB NO.png

S32K314, S32K324 and S32K344

Flash Bank Base address Size J-Link Support
Code flash 0 0x00400000 Up to 1 MB YES.png
Code flash 1 0x00500000 Up to 1 MB YES.png
Code flash 2 0x00600000 Up to 1 MB YES.png
Code flash 3 0x00700000 Up to 1 MB YES.png
Data flash 0x10000000 Up to 128 KB YES.png
UTEST 0x1B000000 Up to 8 KB NO.png

S32K358 and S32K388

Flash Bank Base address Size J-Link Support
Code flash 0 0x00400000 Up to 2 MB YES.png
Code flash 1 0x00600000 Up to 2 MB YES.png
Code flash 2 0x00800000 Up to 2 MB YES.png
Code flash 3 0x00A00000 Up to 2 MB YES.png
Data flash 0x10000000 Up to 128 KB YES.png
UTEST 0x1B000000 Up to 8 KB NO.png

ECC RAM

The ITCM and DTCM must be properly initialized with correct ECC before any read operation to avoid any code runaway or software malfucntion or core lockup. ITCM must be initialized with 64-bit writes whereas DTCM can be initialized with 32-bit or 64-bit writes. The following memory ranges are initialized by the J-Link on connect by default. Other ranges needs to be initialized by the application / boot ROM.

Memory Address Size
DTCM0 0x20000000 32 KB
SRAM0 0x20400000 16 KB

HSE activated

In case of HSE firmware is installed, there are two configurations:

  • FULL_MEM (code flash is considered as one region)
  • AB_SWAP (code flash is split into two regions)

In case of FULL_MEM, the HSE is located at the end of the last code flash memory. Access to this region is prohibited.
In case of AP_SWAP is used, the code flash will be split into two regions. In this case, the HSE is available twice (once per region) and located at the end of both regions.

Multi-Core Support

Before proceeding with this article, please check out the generic article regarding Multi-Core Debugging.
The S32K3 family comes with a variety of multi-core options. Some devices from this family feature a secondary core which is disabled after reset / by default. Some of the are available with enabled lockstep mode, only. In below, the debug related multi-core behavior of the J-Link is described for each core:

Main core

Init/Setup

  • Initializes the ECC RAM, see ECC RAM
  • Enables debugging

Reset

  • Device specific reset is performed, see Reset

Attach

  • Attach is not supported because the J-Link initializes certain RAM regions by default

Secondary core(s)

Init/Setup

  • If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence.
  • If the secondary core is not enabled yet, it will be enabled / release from reset

Reset

No reset is performed.

Attach

  • Attach is supported / desired

Reset

The J-Link performs a device specific reset sequence. The reset is executed for the main core, only. Reset of the main core, resets / disables the secondary core if used in parallel.

Note:
The reset pin needs to be connected in order to guarantee a proper reset.

Limitations

Security / Authentication

There are three different types available in regard to the security. The following table provides an overview of which types are supported and which are not:

Silicon type Info J-Link Support
E5 Configured for Secure boot assist flash (SBAF) YES.png
E6 Configured for secure application debug with password authentication. NO.png
E7 Configured for secure application debug with challenge/response authentication. NO.png


SystemView

With J-Link software V7.84e ECC RAM handling was added. So it is no longer possible to run a debug session in parallel with SystemView, as the connect from SystemView will reinitialize the ECC RAM init and overwrite the RTT buffers. To avoid this the following .JLinkScript file must be added to SystemView.

S32K3xx_SystemView.JLinkScript

How to add a .JLinkScript to SystemView is explained here: J-Link_script_files#SystemView

Evaluation Boards

Example Application

Note:
The example has been tested on the S32K3X4EVB but it should run on any S32K344 based hardware.

Tracing on NXP S32K344

Minimum requirements

In order to use trace on the NXP S32K344 MCU devices, the following minimum requirements have to be met:

  • J-Link software version V7.70c or later
  • Ozone V3.26h or later (if streaming trace and / or the sample project from below shall be used)
  • J-Trace PRO (for Cortex-M) HW version V1.0 or later for streaming trace

To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.

Streaming trace

The project has been tested with the minimum requirements mentioned above and the following two eval board:

Trace buffer (TMC/ETB)

The project below is utilizing the on-chip trace buffer (it is not meant for streaming trace) and works with any NXP S32K344 board.

Tested Hardware

NXP S32K3X4EVB-Q257
NXP S32K3X4EVB-T172

Specifics/Limitations

The S32K3X4EVB_T172 needs some solder bridges closed and resistors removed for all 4 trace data pins to work. For more information about this see the board specific schematics.

Reference trace signal quality

The following pictures show oscilloscope measurements of trace signals output by the NXP S32K3X4EVB-Q257 using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.

Trace clock signal quality

The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.

Trace clock signal quality

Rise time

The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.

TCLK rise time

Setup time

The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.

TD0 setup time