Difference between revisions of "Nordic Semiconductor nRF91xx"

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(Created page with "__TOC__ The nRF91 series is a Cellular IoT SiPs from Nordic Semiconductor using the Arm Cortex-M33 as a dedicated application processor, fully programmable for the user. The n...")
 
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__TOC__
 
__TOC__
The nRF91 series is a Cellular IoT SiPs from Nordic Semiconductor using the Arm Cortex-M33 as a dedicated application processor, fully programmable for the user. The nRF91x1 family is supported since J-Link software version V7.92m.
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The nRF91 series is a Cellular IoT SiPs from Nordic Semiconductor using the ARM Cortex-M33 as a dedicated application processor, fully programmable for the user. The nRF91x1 family is supported since J-Link software version V7.92m.
 
==Internal Flash==
 
==Internal Flash==
 
===Supported Regions===
 
===Supported Regions===
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==Limitations==
 
==Limitations==
 
=== Security / Authentication ===
 
=== Security / Authentication ===
nRF91 Series uses special Debug Locking Mechanism. To gain access to Debugging features the following steps should be performed:
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nRF91 Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed:
1) UICR Registers should be configured to Enable Debug Port.
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1) UICR registers should be configured to enable debug port.
2) User application should set corresponding registers to open access to Debug Port.
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2) User application should set corresponding registers to open access to debug port.
   
Optionally J-Link can perform a full Chip erase, to temporarily reopen Debug Access until next Power Reset.
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Optionally J-Link can perform a full chip erase, to temporarily reopen debug access until next power reset.
   
 
==Evaluation Boards==
 
==Evaluation Boards==

Revision as of 13:33, 8 November 2023

The nRF91 series is a Cellular IoT SiPs from Nordic Semiconductor using the ARM Cortex-M33 as a dedicated application processor, fully programmable for the user. The nRF91x1 family is supported since J-Link software version V7.92m.

Internal Flash

Supported Regions

nRF9131, nRF9161

Flash Bank Base address Size J-Link Support
Code flash 0x00000000 Up to 1 MB YES.png
UICR Config 0x00FF8000 Up to 256 B YES.png
UICR OTP Bytes 0x00FF8108 Up to 760 B YES.png
UICR KeySlots 0x00FF8400 Up to 10240 B NO.png

SRAM

Memory Address Size
SRAM 0x20000000 256 KB

Limitations

Security / Authentication

nRF91 Series uses special debug locking mechanism. To gain access to debugging features the following steps should be performed: 1) UICR registers should be configured to enable debug port. 2) User application should set corresponding registers to open access to debug port.

Optionally J-Link can perform a full chip erase, to temporarily reopen debug access until next power reset.

Evaluation Boards