Difference between revisions of "ONSemi RSL10"
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The RSL10 family from ON Semiconductor is an ultra-low-power SoC designed for use in high−performance applications focused on wearable and medical applications. The SoC features a Cortex-M3 core and supports bluetooth low energy technology and any 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. |
The RSL10 family from ON Semiconductor is an ultra-low-power SoC designed for use in high−performance applications focused on wearable and medical applications. The SoC features a Cortex-M3 core and supports bluetooth low energy technology and any 2.4 GHz proprietary protocol stacks, without sacrificing power consumption. |
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| + | ==Debug Support== |
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| + | J-Link supports debugging and programming of the following memory regions. |
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==On-Chip Memory Regions== |
==On-Chip Memory Regions== |
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The internal flash is divided into 5 different regions: |
The internal flash is divided into 5 different regions: |
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| − | '''NOTE:''' |
+ | '''NOTE:''' J-Link supports the Main Flash as well as NVR1 - NVR3. |
==Reset== |
==Reset== |
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| − | It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which |
+ | It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which makes sure that CPU is halted right before the target application but after boot ROM. |
==Evaluation Boards== |
==Evaluation Boards== |
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*ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP |
*ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP |
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| + | ==Example Application== |
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| + | *ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP#Example_Project |
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| − | == Example Application== |
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| − | The following example project was created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the ON Semiconductor RSL10 SiP EVB V1.2. It is a simple Hello World sample linked into the internal flash. |
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| − | '''SETUP:''' |
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| − | *J-Link software: V6.89c |
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| − | *Embedded Studio: V5.10b |
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| − | *Hardware: ON Semiconductor RSL10 SiP EVB V1.2 |
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| − | *Link: [[File:ONSemi_RSL10_TestProject_ES_V510b.zip]] |
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Latest revision as of 09:00, 9 June 2023
The RSL10 family from ON Semiconductor is an ultra-low-power SoC designed for use in high−performance applications focused on wearable and medical applications. The SoC features a Cortex-M3 core and supports bluetooth low energy technology and any 2.4 GHz proprietary protocol stacks, without sacrificing power consumption.
Debug Support
J-Link supports debugging and programming of the following memory regions.
On-Chip Memory Regions
The internal flash is divided into 5 different regions:
| Instance Name | Size (bytes) | Memory region |
|---|---|---|
| Main Flash | 393216 | 0x00100000 - 0x0015FFFF |
| Non-Volatile Record (NVR) 1 | 2048 | 0x00080000 - 0x000807FF |
| Non-Volatile Record (NVR) 2 | 2048 | 0x00080800 - 0x00080FFF |
| Non-Volatile Record (NVR) 3 | 2048 | 0x00081000 - 0x000807FF |
| Non-Volatile Record (NVR) 4 (Manufacturing Test) |
1024 | 0x00081800 - 0x00080BFF |
NOTE: J-Link supports the Main Flash as well as NVR1 - NVR3.
Reset
It seems like a normal reset via SYSRESETREQ & VECTRESET bit does not work properly on this device. Therefore, the J-Link software performs a specific reset which makes sure that CPU is halted right before the target application but after boot ROM.
Evaluation Boards
- ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP
Example Application
- ON Semiconductor RSL10 SiP evaluation board: https://wiki.segger.com/ONSemi_RSL10_SiP#Example_Project
