Difference between revisions of "Raspberry Pi RP2040"

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| Pins (dedicated) || 6 SPI IOs
 
| Pins (dedicated) || 6 SPI IOs
 
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For further information please refer to the [https://www.raspberrypi.org/documentation/pico/getting-started/ Raspberry Pi Pico web page]
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For further information please refer to the [https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html Raspberry Pi RP2040 web page]
   
 
== J-Link Support ==
 
== J-Link Support ==
 
The Raspberry Pi RP2040 is fully supported by J-Link.
 
The Raspberry Pi RP2040 is fully supported by J-Link.
Support was implemented with [[J-Link Software and Documentation Pack | J-Link Software Pack]] V6.96.
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* Support was implemented with [[J-Link Software and Documentation Pack | J-Link Software Pack]] V6.96.
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* It is recommended to always use the most recent version of the J-Link software as the software is continuously improved and any reported bugs are fixed
   
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== ROM Bootloader ==
'''Note:'''There seems to be a chip specific issue when trying to reconnect to the target device or if you switch connecttion to the second core. Instead of power cycling this can be solved by connecting Reset (Pin 15) from the J-Link to Pin "RUN" (Chip enable/Reset) of the RP2040.
 
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The RP2040 comes with a bootloader in ROM. More information on ROM bootloaders in general can be found here: [[ROM Bootloader | ROM Bootloader]].<br>
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For a documentation of the RP2040 boot sequence, refer to the [https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf RP2040 datasheet]. <br>
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When working with the RP2040, the following must be considered in regard to its ROM bootloader:<br>
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The ROM BTL expects a "flash second stage" (aka. "2nd stage bootloader") in the external QSPI flash.<br>
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The ROM BTL verifies that such a valid 2nd stage BTL is present by calculating a [[CRC |CRC]] over the first 252 bytes of the QSPI flash and comparing it against the 4 bytes following those 252 bytes. Only if the calculated CRC matches the CRC value in flash, the ROM BTL will jump to user application code (i.e. the 2nd stage BTL).
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The 2nd stage BTL is not part of the application image and as such can be adapted by the user. It usually performs some additional setup to enable XIP from the QSPI flash or similar before jumping to the "actual" start of application.
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== Reset ==
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As explained [[#ROM Bootloader| above]], the RP2040 includes a boot ROM which needs to be executed after reset in order to guarantee proper functionality.<br>
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Due to the behavior of the ROM BTL, J-Link performs a device specific reset which halts at address 0x20041F00, on the first instruction of this so called "flash second stage" aka. 2nd stage BTL.
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== RAM Debugging ==
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As explained [[#ROM Bootloader| above]], the RP2040 includes a boot ROM which needs to be executed after reset in order to guarantee proper functionality.<br>
  +
Due to the behavior of the ROM BTL, it is necessary to download a valid 2nd stage BTL into flash, even if only code in RAM should be downloaded and debugged, otherwise the target device might not behave as expected.<br>
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For an example setup of RAM project for the RP2040, refer to the section "[[#RAM Projects |RAM Projects]]" below
   
 
== Evaluation boards ==
 
== Evaluation boards ==
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== Sample projects ==
 
== Sample projects ==
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SEGGER Embedded Studio provides a RP2040 board support package for the RP2040 Pico.
 
SEGGER Embedded Studio provides a RP2040 board support package for the RP2040 Pico.
 
It is easily adjusted to all other available RP2040 boards, especially, as the QSPI pin-out is not modifiable.
 
It is easily adjusted to all other available RP2040 boards, especially, as the QSPI pin-out is not modifiable.
 
Additionally, the articles listed under [[#Evaluation boards | Evaluation boards]] all provide sample applications.
 
Additionally, the articles listed under [[#Evaluation boards | Evaluation boards]] all provide sample applications.
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===RAM Projects===
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To run the following example projects the following prerequisites need to be met:
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* [https://www.segger.com/downloads/jlink/#J-LinkSoftwareAndDocumentationPack J-Link software] V7.64e or later
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* J-Link HW revision 11 or later (J-Link EDU Mini and J-Trace PRO V1 or later also supported)
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* [https://www.segger.com/products/development-tools/embedded-studio/ SEGGER Embedded Studio for ARM] V6.30 or later
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Core0: [[Media:RaspberryPi_RP2040_Core0.zip|RaspberryPi_RP2040_Core0.zip]]

Latest revision as of 14:24, 11 May 2022

This article covers the Raspberry Pi RP2040 device, an arm Cortex-M0+ dualcore MCU with up to 133 MHz Clock. It is the first MCU designed and published by Raspberry Pi. The RP2040 is present on the Raspberry Pi Pico evaluation board.

Features (selection)

Stat Specification
Core Dualcore M0+
RAM 264kB SRAM
Internal flash No internal flash (ext. QSPI supported)
Pins (multifunc) 30 GPIOs
Pins (dedicated) 6 SPI IOs

For further information please refer to the Raspberry Pi RP2040 web page

J-Link Support

The Raspberry Pi RP2040 is fully supported by J-Link.

  • Support was implemented with J-Link Software Pack V6.96.
  • It is recommended to always use the most recent version of the J-Link software as the software is continuously improved and any reported bugs are fixed

ROM Bootloader

The RP2040 comes with a bootloader in ROM. More information on ROM bootloaders in general can be found here: ROM Bootloader.
For a documentation of the RP2040 boot sequence, refer to the RP2040 datasheet.

When working with the RP2040, the following must be considered in regard to its ROM bootloader:
The ROM BTL expects a "flash second stage" (aka. "2nd stage bootloader") in the external QSPI flash.
The ROM BTL verifies that such a valid 2nd stage BTL is present by calculating a CRC over the first 252 bytes of the QSPI flash and comparing it against the 4 bytes following those 252 bytes. Only if the calculated CRC matches the CRC value in flash, the ROM BTL will jump to user application code (i.e. the 2nd stage BTL).

The 2nd stage BTL is not part of the application image and as such can be adapted by the user. It usually performs some additional setup to enable XIP from the QSPI flash or similar before jumping to the "actual" start of application.

Reset

As explained above, the RP2040 includes a boot ROM which needs to be executed after reset in order to guarantee proper functionality.
Due to the behavior of the ROM BTL, J-Link performs a device specific reset which halts at address 0x20041F00, on the first instruction of this so called "flash second stage" aka. 2nd stage BTL.

RAM Debugging

As explained above, the RP2040 includes a boot ROM which needs to be executed after reset in order to guarantee proper functionality.
Due to the behavior of the ROM BTL, it is necessary to download a valid 2nd stage BTL into flash, even if only code in RAM should be downloaded and debugged, otherwise the target device might not behave as expected.
For an example setup of RAM project for the RP2040, refer to the section "RAM Projects" below

Evaluation boards

There are multiple RP2040 evaluation boards. For all of the ones listed below, sample applications are available.

Sample projects

SEGGER Embedded Studio provides a RP2040 board support package for the RP2040 Pico. It is easily adjusted to all other available RP2040 boards, especially, as the QSPI pin-out is not modifiable. Additionally, the articles listed under Evaluation boards all provide sample applications.

RAM Projects

To run the following example projects the following prerequisites need to be met:

Core0: RaspberryPi_RP2040_Core0.zip