Difference between revisions of "Renesas ASSP EASY"
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| − | The ''' |
+ | The '''Renesas ASSP easy''' are RISC-V based microcontrollers. |
__TOC__ |
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! Flash Bank || Base address !! Size || J-Link Support |
! Flash Bank || Base address !! Size || J-Link Support |
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| − | | |
+ | | Code Flash || 0x00000000 || up to 128 KB || style="text-align:center;"| {{YES}} |
| − | |} |
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| − | |||
| − | ====ECC Flash [OPTIONAL]==== |
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| − | *Describe ECC Flash restriction here. |
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| − | |||
| − | ===QSPI Flash=== |
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| − | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| − | J-Link supports multiple pin configurations for [DEVICE]. The default loader is marked in '''bold'''. |
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| − | {| class="seggertable" |
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|- |
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| + | | Config Flash || 0x01010008 || up tp 44 B || style="text-align:center;"| {{YES}} |
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| − | ! Device !! Base address !! Maximum size !! Supported pin configuration |
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|- |
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| + | | Data Flash || 0x40100000 || up to 4 KB || style="text-align:center;"| {{YES}} |
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| − | | [DEVICE]|| [BANK_BASE_ADDRESS] || [MAX_SPI_FLASH_SIZE] MB || |
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| − | *'''[LOADER_NAME]''' |
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| − | *[LOADER_NAME] |
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| − | *[LOADER_NAME] |
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|} |
|} |
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| − | ==ECC RAM |
+ | ==ECC RAM== |
| + | *Device has ECC RAM which has to be initialized before use. |
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| − | *Describe ECC RAM restriction here. |
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| − | |||
| − | ==Vector Table Remap [OPTIONAL]== |
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| − | *Describe Vector Table Remap here.. |
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==Watchdog Handling== |
==Watchdog Handling== |
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| − | *The device |
+ | *The device has 2 watchdogs. |
| + | *Both watchdogs are fed during flash programming. |
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| − | *The device has a watchdog [WATCHDOGNAME]. |
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| − | *The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| − | |||
| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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| + | *On Connect, the RAM is initialized. |
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| + | |||
===Reset=== |
===Reset=== |
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| − | *The device uses normal |
+ | *The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_6 | here]]. |
| − | *The device uses Cortex-M Core reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_1:_Core | here]]. |
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| − | *The device uses Cortex-M Rest Pin, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_2:_ResetPin | here]]. |
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| − | *The device uses Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-A devices | here]]. |
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| − | *The device uses Cortex-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for Cortex-R devices | here]]. |
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| − | *The device uses ARMv8-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-A devices | here]]. |
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| − | *The device uses ARMv8-R reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Strategies for ARMv8-R devices | here]]. |
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| − | *The device uses custom reset:..... |
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==Limitations== |
==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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| − | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| + | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
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| − | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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==Example Application== |
==Example Application== |
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| + | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
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| − | *[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]] |
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| − | |||
| − | == Tracing on [SiliconVendor] [DeviceFamily] == |
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| − | This section describes how to get started with trace on the [SiliconVendor] [DeviceFamily] MCUs. |
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| − | This section assumes that there is already a basic knowledge about trace in general (what is trace, what different implementations of trace are there, etc.). |
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| − | If this is not the case, we recommend to read '''Trace''' chapter in the J-Link User Manual (UM08001). |
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| − | {{Note|1= |
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| − | * The sample projects come with a pre-configured project file for Ozone that runs out-of-the box. |
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| − | * The following sample project is designed to be used with J-Trace PRO for streaming trace, J-Link Plus for buffer tracing (TMC/ETB trace) and Ozone to demonstrate streaming trace. |
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| − | * In order to rebuild the sample project, [https://www.segger.com/embedded-studio.html SEGGER Embedded Studio] can be used. |
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| − | * The examples are shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
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| − | ** To create your own .JLinkScriptfile you can use the following guide as reference: [[How_to_configure_JLinkScript_files_to_enable_tracing]] |
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| − | }} |
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| − | |||
| − | === Tracing on [SiliconVendor] [DeviceName] ([Boardname]-optional) === |
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| − | ==== Minimum requirements ==== |
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| − | In order to use trace on the [SiliconVendor] [DeviceName] MCU devices, the following minimum requirements have to be met: |
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| − | * J-Link software version Vx.xxx or later |
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| − | * Ozone Vx.xxx or later (if streaming trace and / or the sample project from below shall be used) |
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| − | * J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace |
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| − | * J-Link Plus V12 or later for TMC/ETB trace |
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| − | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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| − | ==== Streaming trace ==== |
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| − | The project below has been tested with the minimum requirements mentioned above and a ''[Boardname]''. |
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| − | *'''Example project:''' [[Media:ST_STM32H7_Trace_Tutorial_Project.zip | ST_STM32H7_Trace_Tutorial_Project.zip]] |
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| − | ==== Trace buffer (TMC/ETB) ==== |
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| − | The project below is utilizing the on-chip trace buffer (it is '''not''' meant for streaming trace). |
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| − | *'''Example Project:''' [[Media:ST_STM32H7_TraceBuffer_Tutorial_Project.zip | ST_STM32H7_TraceBuffer_Tutorial_Project.zip]] |
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| − | ==== Tested Hardware ==== |
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| − | [[File:STM32H7_trace_reference_board.png|none|thumb|SEGGER STM32H7 Trace Reference Board]] |
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| − | ==== Reference trace signal quality ==== |
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| − | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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| − | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
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| − | If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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| − | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| − | ===== Trace clock signal quality ===== |
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| − | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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| − | [[File:STM32H7_TRB_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
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| − | ===== Rise time ===== |
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| − | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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| − | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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| − | [[File:STM32H7_TRB_Risetime_TCLK.png|none|thumb|TCLK rise time]] |
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| − | ===== Setup time ===== |
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| − | The setup time shows the relative setup time between a trace data signal and trace clock. |
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| − | The measurement markers are set at 50% of the expected voltage level respectively. |
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| − | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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| − | [[File:STM32H7_TRB_Setuptime_TD0.png|none|thumb|TD0 setup time]] |
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Latest revision as of 17:47, 18 March 2024
The Renesas ASSP easy are RISC-V based microcontrollers.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code Flash | 0x00000000 | up to 128 KB | 
|
| Config Flash | 0x01010008 | up tp 44 B |
|
| Data Flash | 0x40100000 | up to 4 KB |
|
ECC RAM
- Device has ECC RAM which has to be initialized before use.
Watchdog Handling
- The device has 2 watchdogs.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, the RAM is initialized.
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Limitations
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
