Difference between revisions of "Renesas ASSP EASY"
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==ECC RAM== |
==ECC RAM== |
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| − | *Device has ECC RAM which has to be initialized before use. |
+ | *Device has ECC RAM which has to be initialized before use. |
| − | |||
==Watchdog Handling== |
==Watchdog Handling== |
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| − | *The device |
+ | *The device has 2 watchdogs. |
| + | *Both watchdogs are fed during flash programming. |
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| − | *The device has a watchdog [WATCHDOGNAME]. |
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| − | *The watchdog is fed during flash programming. |
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| − | *If the watchdog is enabled, it is turned off during flash programming and turned back on afterwards. |
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| − | |||
| − | ==Multi-Core Support [OPTIONAL]== |
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| − | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | The [DeviceFamily]family comes with a variety of multi-core options.<br> |
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| − | Some devices from this family feature a secondary core which is disabled after reset / by default.<br> |
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| − | Some of the are available with enabled ''lockstep'' mode, only. <br> |
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| − | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | ===Main core=== |
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| − | ====Init/Setup==== |
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| − | *Initializes the ECC RAM, see [[XXX | XXX]] |
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| − | *Enables debugging |
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| − | ====Reset==== |
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| − | *Device specific reset is performed, see [[XXX | XXX]] |
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| − | ====Attach==== |
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| − | *Attach is not supported because the J-Link initializes certain RAM regions by default |
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| − | ===Secondary core(s)=== |
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| − | ====Init/Setup==== |
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| − | *If the main core session has not been started / debugging is not enabled yet, the secondary core executes the enable debug sequence. |
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| − | *If the secondary core is not enabled yet, it will be enabled / release from reset |
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| − | ====Reset==== |
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| − | No reset is performed. |
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| − | ====Attach==== |
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| − | *Attach is supported / desired |
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==Device Specific Handling== |
==Device Specific Handling== |
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===Connect=== |
===Connect=== |
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| + | *On Connect, the RAM is initialized. |
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| + | |||
===Reset=== |
===Reset=== |
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*The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_6 | here]]. |
*The device uses normal RISC-V reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_6 | here]]. |
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==Limitations== |
==Limitations== |
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| − | ===Dual Core Support=== |
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| − | Some XXX devices feature a second core. Right now, the J-Link software does support the main core, only. Support for the second core is planned for future versions. |
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===Attach=== |
===Attach=== |
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Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
Attach is not supported by default because the J-Link initializes certain RAM regions by default. |
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| − | ===Security=== |
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==Evaluation Boards== |
==Evaluation Boards== |
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| + | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
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| − | *[[WikiTemplateEvalBoard|[SiliconVendor] [EvalBoardName]]] |
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==Example Application== |
==Example Application== |
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| + | *[[Renesas_FPB-R9A02G021| FPB-R9A02G021]] |
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| − | *[[WikiTemplateEvalBoard#Example_Project | [SiliconVendor] [EvalBoardName]]] |
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Latest revision as of 17:47, 18 March 2024
The Renesas ASSP easy are RISC-V based microcontrollers.
Contents
Flash Banks
Internal Flash
| Flash Bank | Base address | Size | J-Link Support |
|---|---|---|---|
| Code Flash | 0x00000000 | up to 128 KB | 
|
| Config Flash | 0x01010008 | up tp 44 B |
|
| Data Flash | 0x40100000 | up to 4 KB |
|
ECC RAM
- Device has ECC RAM which has to be initialized before use.
Watchdog Handling
- The device has 2 watchdogs.
- Both watchdogs are fed during flash programming.
Device Specific Handling
Connect
- On Connect, the RAM is initialized.
Reset
- The device uses normal RISC-V reset, no special handling necessary, like described here.
Limitations
Attach
Attach is not supported by default because the J-Link initializes certain RAM regions by default.
