Difference between revisions of "i.MX6SoloX"
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| + | The '''NXP iMX6SoloX''' are multi-core MCUs composed of a Cortex-M4 and Cortex-A9 core. |
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| − | Multi-core support for iMX6SX (Solo X) |
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| − | J-Link script files are necessary to connect to the A9 and M4 core of the iMX6SX (SoloX) MCU. |
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| + | ==Flash Banks== |
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| − | A9 core: |
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| + | ===QSPI Flash=== |
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| − | [[File:iMX6SoloX_Connect_CortexA9.JLinkScript]] |
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| + | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
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| + | J-Link supports the following pin configurations for iMX6SoloX: |
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| + | {| class="seggertable" |
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| − | M4 core: |
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| − | [[File:iMX6SoloX_Connect_CortexM4.JLinkScript]] |
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| − | |||
| − | How to use script files: |
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| − | Please refer to J-Link User Guide (UM08001), chapter 5.10 "J-Link script files" |
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| − | |||
| − | Startup procedure is: |
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| − | 1) Start debug session that connects to A9 and let it run the application to the point that enables the M4 |
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| − | 2) Start debug session that connects to M4 |
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| − | [...] |
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| − | x) Close debug session that connects to M4 |
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| − | x + 1) Close debug session that connects to A9 |
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| − | |||
| − | '''Important!''' |
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| − | On the SoloX the M4 cannot be independently debugged without having something running on the A9 that enables the M4. |
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| − | Since Freescale removed some features from the i.MX6 to the SoloX, it is no longer possible to easily enable the M4 from the debug interface and so being able to debug it completely independent from the A9. |
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| − | |||
| − | == iMX6SX (Q)SPI support == |
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| − | The NXP iMX6SX device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined but different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm, which allows to program any common (Q)SPI flash, connected to the Quad-SPI interface of the NXP iMX6SX device. The flash algorithm is based on the Open Flashloader concept so it can easily exchanged if a pin configuration, different from the one used in the example flash algorithm, is required. In such cases, please get in touch with SEGGER directly (support@segger.com). |
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| − | === Example Implementation 1 (SABRE evaluation board) === |
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| − | As described above, the reference flash algorithm is based on the Open Flashloader and therefore needs to be added manually using a JLinkDevices.xml file. An example JLinkDevices.xml entry as well as the used pinout in the example flash algorithm is given below. This example assumes a Micron N25Q256A1 (32MB flash) connected to the Quad-SPI interface of the iMX6SX. For further information regarding the Open Flashloader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter ''10 Open Flash Loader''. |
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| − | |||
| − | ====Quad-SPI Interface Pins==== |
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| − | The following QSPI interface is used on the iMX6SX SABRE evaluation board to interface the (Q)SPI flash. |
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| − | {| class="wikitable" |
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|- |
|- |
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! Alternate function !! Port / Pin |
! Alternate function !! Port / Pin |
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| + | ==Multi-Core Support == |
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| − | ====JLinkDevices.xml==== |
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| + | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
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| − | <Database> |
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| + | The iMX6SoloX family feature a Cortex-A9 and Cortex-M4 core.<br> |
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| − | <Device> |
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| + | In below, the debug related multi-core behavior of the J-Link is described for each core: |
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| − | <ChipInfo Vendor="NXP" |
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| + | ===Cortex-A9=== |
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| − | JLinkScriptFile="Devices\NXP\iMX6SoloX_Connect_CortexA9.JLinkScript" |
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| + | ====Init/Setup==== |
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| − | Name="MCIMX6X1_A9" |
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| + | *Enables debugging |
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| − | WorkRAMAddr="0x00900000" |
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| + | ====Reset==== |
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| − | WorkRAMSize="0x00020000" |
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| + | *No Reset is performed. |
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| − | Core="JLINK_CORE_CORTEX_A9"/> |
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| + | ===Secondary core(s)=== |
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| − | <FlashBankInfo Name="QSPI Flash" |
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| + | ====Init/Setup==== |
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| − | BaseAddr="0x70000000" |
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| + | *Enables debugging |
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| − | MaxSize="0x02000000" |
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| + | ====Reset==== |
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| − | Loader="NXP_iMX6SX_SABRE_Board_QSPI.elf" |
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| + | *No reset is performed. |
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| − | LoaderType="FLASH_ALGO_TYPE_OPEN" /> |
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| − | </Device> |
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| − | </Database> |
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| − | *[[File:NXP_iMX6SX_SABRE_Board_QSPI_JLinkDevicesXML.zip]] |
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| − | |||
| − | ====Flash algorithm (*.elf)==== |
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| − | This file contains the program routines used by the J-Link DLL during flash programming. |
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| − | *[[File:NXP_iMX6SX_SABRE_Board_QSPI_ReferenceFlashAlgorithm.zip]] |
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| − | ====IAR example project==== |
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| − | The example project contains a simple counter loop which is linked into the (Q)SPI flash memory region @ address 0x70000000. The project includes the JLinkDevices.xml file as well as the NXP_iMX6SX_SABRE_Board_QSPI.elf. It runs out-of-the-box. Please note, that IAR EWARM must at least use the J-Link DLL version V6.10m. |
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| − | *[[File:NXP_iMX6SX_SABRE_Board_QSPI_IARV6405.zip]] |
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| − | |||
| − | === Example Implementation 2 === |
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| − | As described above, the reference flash algorithm is based on the Open Flashloader and therefore needs to be added manually using a JLinkDevices.xml file. An example JLinkDevices.xml entry as well as the used pinout in the example flash algorithm is given below. This example assumes a Spansion S25FL256S (32MB flash) connected to the Quad-SPI interface of the iMX6SX. For further information regarding the Open Flashloader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter ''10 Open Flash Loader''. |
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| − | |||
| − | ====Quad-SPI Interface Pins==== |
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| − | The following QSPI interface is used to interface the (Q)SPI flash. |
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| − | {| class="wikitable" |
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| − | |- |
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| − | ! Alternate function !! Port / Pin |
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| − | |- |
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| − | | QSPI1A_DATA0 || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0 |
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| − | |- |
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| − | | QSPI2A_DATA1 || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1 |
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| − | |- |
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| − | | QSPI2A_DATA2 || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2 |
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| − | |- |
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| − | | QSPI2A_DATA3 || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3 |
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| − | |- |
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| − | | QSPI1A_SS0_B || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B |
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| − | |- |
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| − | | QSPI1A_SCLK || IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK |
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| − | |} |
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| − | |||
| − | ====JLinkDevices.xml==== |
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| + | ==Evaluation Boards== |
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| − | (see ''Example Implementation 2'' above) |
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| + | *[[NXP iMX6SX SABRE]] |
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| + | ==Example Application== |
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| − | ====Flash algorithm (*.elf)==== |
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| + | *[[NXP iMX6SX SABRE#Example_Project | NXP iMX6SX SABRE]] |
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| − | This file contains the program routines used by the J-Link DLL during flash programming. |
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| − | *[[File:NXP_custom_Board_FlashAlgorithm.zip]] |
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Latest revision as of 17:36, 23 February 2024
The NXP iMX6SoloX are multi-core MCUs composed of a Cortex-M4 and Cortex-A9 core.
Contents
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports the following pin configurations for iMX6SoloX:
| Alternate function | Port / Pin |
|---|---|
| QSPI2A_SS0_B | IOMUXC_SW_MUX_CTL_PAD_NAND_ALE |
| QSPI2A_DATA2 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B |
| QSPI2A_DATA3 | IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B |
| QSPI2A_SCLK | IOMUXC_SW_MUX_CTL_PAD_NAND_CLE |
| QSPI2A_DATA1 | IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B |
| QSPI2A_DATA0 | IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B |
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
The iMX6SoloX family feature a Cortex-A9 and Cortex-M4 core.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-A9
Init/Setup
- Enables debugging
Reset
- No Reset is performed.
Secondary core(s)
Init/Setup
- Enables debugging
Reset
- No reset is performed.
