i.MX7ULP
The NXP i.MX7ULP are multicore MCUs consisting of a Cortex-M4 and Cortex-A7.
Contents
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
Device | Base address | Maximum size |
---|---|---|
MCIMX7U3_M4 MCIMX7U5_M4 |
0x04000000 | 128 MB |
MCIMX7U3_A7 MCIMX7U5_A7 |
0xC0000000 | 128 MB |
Watchdog Handling
- The watchdogs WDOG0, WDOG1 and WDOG2 are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M4
Init/Setup
- Enables debugging
- Disables MPU
Reset
No reset is performed.
Cortex-A7
Init/Setup
Core is enabled by setting A7_CORE1_ENABLE bit in SRC_A7RCR1 register.
Reset
No reset is performed.