Difference between revisions of "i.MX7ULP"
(→iMX7ULP (Q)SPI support) |
(→Flash Banks) |
||
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
| + | The '''NXP i.MX7ULP''' are multicore MCUs consisting of a Cortex-M4 and Cortex-A7. |
||
| − | == iMX7ULP (Q)SPI support == |
||
| + | __TOC__ |
||
| − | The NXP iMX7ULP device series comes with a QUADSPI controller which allows memory mapped read accesses to any (Q)SPI flash, connected to the Quad-SPI interface of the MCU. This allows the J-Link DLL to support flash programming through the Quad-SPI interface. Unfortunately, there is no generic way how to implement flash programming because the used pins to connect the SPI flash is not defined but different pins can be used for the same QUADSPI alternate function and therefore, for each configuration, a slightly different RAMCode (different pin initialization / flash size) is required. We have developed a flash algorithm, which allows to program any common (Q)SPI flash, connected to the Quad-SPI interface of the NXP iMX7ULP device. The flash algorithm is based on the Open Flashloader concept so it can easily exchanged if a pin configuration, different from the one used in the example flash algorithm, is required. In such cases, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
||
| − | === Example Implementation (iMX7ULP-EVK-SOM with base board) === |
||
| − | As described above, the reference flash algorithm is based on the Open Flashloader and therefore needs to be added manually using a JLinkDevices.xml file. An example JLinkDevices.xml entry as well as the used pinout in the example flash algorithm is given below. This example assumes a Macronix MX25R6435F(8MB flash) connected to the Quad-SPI interface of the iMX7ULP. For further information regarding the Open Flashloader and how to use the JLinkDevices.xml file, please refer to the J-Link User Manual (UM08001), chapter ''10 Open Flash Loader''. |
||
| + | ==Flash Banks== |
||
| − | ====Quad-SPI Interface Pins==== |
||
| + | ===QSPI Flash=== |
||
| + | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
||
| + | {| class="seggertable" |
||
| + | |- |
||
| + | ! Device !! Base address !! Maximum size |
||
| + | |- |
||
| + | | MCIMX7U3_M4<br>MCIMX7U5_M4 || 0x04000000 || 128 MB |
||
| + | |- |
||
| + | | MCIMX7U3_A7<br>MCIMX7U5_A7 || 0xC0000000 || 128 MB |
||
| + | |} |
||
The following QSPI interface is used on the iMX7ULP-EVK-SOM board to interface the (Q)SPI flash. |
The following QSPI interface is used on the iMX7ULP-EVK-SOM board to interface the (Q)SPI flash. |
||
| − | {| class=" |
+ | {| class="seggertable" |
|- |
|- |
||
! Alternate function !! Port / Pin |
! Alternate function !! Port / Pin |
||
| Line 23: | Line 31: | ||
|} |
|} |
||
| + | ==Watchdog Handling== |
||
| − | ====JLinkDevices.xml==== |
||
| + | *The watchdogs WDOG0, WDOG1 and WDOG2 are fed during flash programming. |
||
| − | <Database> |
||
| + | |||
| − | <Device> |
||
| + | ==Multi-Core Support == |
||
| − | <ChipInfo Vendor="NXP" |
||
| + | Before proceeding with this article, please check out the generic article regarding Multi-Core debugging [[Multi-Core_Debugging | here]].<br> |
||
| − | JLinkScriptFile="Devices\NXP\iMX7ULP\NXP_iMX7ULP_Connect_CortexA7.JLinkScript" |
||
| + | In below, the debug related multi-core behavior of the J-Link is described for each core: |
||
| − | Name="MCIMX7U5_A7" |
||
| + | ===Cortex-M4=== |
||
| − | WorkRAMAddr="0x20000000" |
||
| + | ====Init/Setup==== |
||
| − | WorkRAMSize="0x00010000" |
||
| + | *Enables debugging |
||
| − | Core="JLINK_CORE_CORTEX_A7"/> |
||
| + | *Disables MPU |
||
| − | <FlashBankInfo Name="QSPI Flash" |
||
| + | ====Reset==== |
||
| − | BaseAddr="0xC0000000" |
||
| + | No reset is performed. |
||
| − | MaxSize="0x10000000" |
||
| + | ===Cortex-A7=== |
||
| − | Loader="NXP_iMX7ULP_BB.elf" |
||
| + | ====Init/Setup==== |
||
| − | LoaderType="FLASH_ALGO_TYPE_OPEN" /> |
||
| + | Core is enabled by setting A7_CORE1_ENABLE bit in SRC_A7RCR1 register. |
||
| − | </Device> |
||
| + | ====Reset==== |
||
| − | </Database> |
||
| + | No reset is performed. |
||
| − | *[[Media:iMX7ULP_EVK_SOM_JLinkDevices.zip|iMX7ULP_EVK_SOM_JLinkDevices.zip]] |
||
| + | |||
| + | ==Evaluation Boards== |
||
| + | *[[NXP MCIMX7ULP-EVK|NXP MCIMX7ULP-EVK]] |
||
| + | ==Example Application== |
||
| − | ====Flash algorithm (*.elf)==== |
||
| + | *[[NXP MCIMX7ULP-EVK#Example_Project | NXP MCIMX7ULP-EVK]] |
||
| − | This file contains the program routines used by the J-Link DLL during flash programming. |
||
| − | *[[Media:IMX7ULP_EVK_SOM_elf.zip|IMX7ULP_EVK_SOM_elf.zip]] |
||
| − | ====Embedded Studio example project==== |
||
| − | The example project contains a simple counter loop which is linked into the (Q)SPI flash memory region @ address 0xC0000000. The project includes the JLinkDevices.xml file as well as the NXP_iMX7ULP_BB.elf. It runs out-of-the-box. Please note, that Embedded Studio 3.20 or later and at least the J-Link DLL version V6.16a must be used. |
||
| − | *[[Media:NXP_iMX7ULP_EVK_SOM_ES_project.zip|NXP_iMX7ULP_EVK_SOM_ES_project.zip]] |
||
Latest revision as of 17:20, 8 March 2024
The NXP i.MX7ULP are multicore MCUs consisting of a Cortex-M4 and Cortex-A7.
Contents
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
| Device | Base address | Maximum size |
|---|---|---|
| MCIMX7U3_M4 MCIMX7U5_M4 |
0x04000000 | 128 MB |
| MCIMX7U3_A7 MCIMX7U5_A7 |
0xC0000000 | 128 MB |
The following QSPI interface is used on the iMX7ULP-EVK-SOM board to interface the (Q)SPI flash.
| Alternate function | Port / Pin |
|---|---|
| QSPIA_SS0_B (AF8) | PTB8 |
| QSPIA_SCLK (AF8) | PTB15 |
| QSPIA_DATA3 (AF8) | PTB16 |
| QSPIA_DATA2 (AF8) | PTB17 |
| QSPIA_DATA1 (AF8) | PTB18 |
| QSPIA_DATA0 (AF8) | PTB19 |
Watchdog Handling
- The watchdogs WDOG0, WDOG1 and WDOG2 are fed during flash programming.
Multi-Core Support
Before proceeding with this article, please check out the generic article regarding Multi-Core debugging here.
In below, the debug related multi-core behavior of the J-Link is described for each core:
Cortex-M4
Init/Setup
- Enables debugging
- Disables MPU
Reset
No reset is performed.
Cortex-A7
Init/Setup
Core is enabled by setting A7_CORE1_ENABLE bit in SRC_A7RCR1 register.
Reset
No reset is performed.
