User contributions
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- 11:13, 18 November 2021 (diff | hist) . . (0) . . File:NXP iMX6DQ Core3.JLinkScript (Alex uploaded a new version of File:NXP iMX6DQ Core3.JLinkScript) (current)
- 11:13, 18 November 2021 (diff | hist) . . (0) . . File:NXP iMX6DQ Core2.JLinkScript (Alex uploaded a new version of File:NXP iMX6DQ Core2.JLinkScript) (current)
- 11:13, 18 November 2021 (diff | hist) . . (0) . . File:NXP iMX6DQ Core1.JLinkScript (Alex uploaded a new version of File:NXP iMX6DQ Core1.JLinkScript) (current)
- 19:14, 12 November 2021 (diff | hist) . . (+2,542) . . N ROMTableScan (Created page with "For ARM CoreSight based systems, by default J-Link will scan the ROM table (and nested ones) to find CoreSight components like for example: * The core debug registers * An Emb...")
- 19:54, 28 October 2021 (diff | hist) . . (+11) . . Using J-Link via WiFi (→Via WiFi bridge)
- 19:54, 28 October 2021 (diff | hist) . . (-57) . . Using J-Link via WiFi (→Via J-Link Remote Server)
- 19:54, 28 October 2021 (diff | hist) . . (0) . . Using J-Link via WiFi (→J-Link BASE or higher)
- 19:53, 28 October 2021 (diff | hist) . . (+56) . . Using J-Link via WiFi (→J-Link PRO and J-Trace PRO (Cortex-M))
- 09:43, 16 September 2021 (diff | hist) . . (-2) . . Software and Hardware Features Overview (→Flasher)
- 09:38, 4 August 2021 (diff | hist) . . (+25) . . Enable J-Link log file (→Enable J-Link Log File)
- 14:43, 19 July 2021 (diff | hist) . . (0) . . Syntacore SCR3
- 14:42, 19 July 2021 (diff | hist) . . (+1,042) . . N Syntacore SCR3 (Created page with "The Syntacore SCR3 is a 32-bit (RV32) core, designed by [https://syntacore.com/page/products/processor-ip/scr3 Syntacore]. __TOC__ = Requirements = * A current J-Link model...")
- 14:42, 19 July 2021 (diff | hist) . . (+28) . . Debug Probes - J-Link & J-Trace (→Syntacore)
- 14:41, 19 July 2021 (diff | hist) . . (-41) . . Syntacore SCR1 (current)
- 14:41, 19 July 2021 (diff | hist) . . (+182) . . Syntacore SCR1
- 14:31, 30 June 2021 (diff | hist) . . (-96) . . Raspberry Pi RP2040 (→J-Link Support)
- 09:26, 30 June 2021 (diff | hist) . . (+70) . . RTT (→RISC-V specifics)
- 09:24, 30 June 2021 (diff | hist) . . (0) . . RTT
- 09:23, 30 June 2021 (diff | hist) . . (+1,322) . . RTT
- 09:05, 30 June 2021 (diff | hist) . . (+222) . . RTT
- 10:19, 15 June 2021 (diff | hist) . . (+26) . . Codasip L10
- 10:18, 15 June 2021 (diff | hist) . . (+641) . . N Codasip H50X (Created page with "The Codasip H50X is a 64-bit (RV64) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: * H50X (no FPU) * H50XF...")
- 10:17, 15 June 2021 (diff | hist) . . (+636) . . N Codasip L50 (Created page with "The Codasip L50 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: * L50 (no FPU) * L50F (i...")
- 10:17, 15 June 2021 (diff | hist) . . (+26) . . Codasip L30
- 10:15, 15 June 2021 (diff | hist) . . (+122) . . Debug Probes - J-Link & J-Trace (→Codasip)
- 14:37, 10 June 2021 (diff | hist) . . (-16) . . CloudBEAR BM-310
- 14:22, 10 June 2021 (diff | hist) . . (+538) . . N Codasip L10 (Created page with "The Codasip L10 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. __TOC__ = Minimum required J-Link software version =...")
- 14:22, 10 June 2021 (diff | hist) . . (+610) . . N Codasip L30 (Created page with "The Codasip L30 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: * L30 (no FPU) * L30F (i...")
- 14:20, 10 June 2021 (diff | hist) . . (+117) . . Debug Probes - J-Link & J-Trace (→CloudBEAR)
- 11:22, 10 June 2021 (diff | hist) . . (+2) . . Debug Probes - J-Link & J-Trace (→CloudBEAR)
- 11:21, 10 June 2021 (diff | hist) . . (+511) . . N CloudBEAR BM-610 (Created page with "The CloudBEAR BM-610 is a 64-bit (RV64) core, designed by [https://cloudbear.ru/products.html CloudBEAR]. __TOC__ = Minimum required J-Link software version = The BM-610 dev...")
- 11:21, 10 June 2021 (diff | hist) . . (+83) . . Debug Probes - J-Link & J-Trace (→Cypress)
- 11:19, 10 June 2021 (diff | hist) . . (+527) . . N CloudBEAR BM-310 (Created page with "The CloudBEAR BM-310 is a 32-bit (RV32) core, designed by [https://cloudbear.ru/products.html CloudBEAR]. __TOC__ = Minimum required J-Link software version = The BM-310 dev...")
- 16:56, 1 June 2021 (diff | hist) . . (+380) . . N SEGGER standard for units of Memory size (Created page with "This article describes the units used by SEGGER for sizes and speeds, in manuals and on the web. __TOC__ = Speed units = * Always metric: Powers of 10 * kB/s = 1000 bytes pe...")
- 11:01, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive S76 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive S76 Standard Core Dev Kit. The SiFive S76 Standard Core Dev Kit implements a SiFive S76 (64-bit RV64) core as a FPGA b...")
- 11:01, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive S51 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive S51 Standard Core Dev Kit. The SiFive S51 Standard Core Dev Kit implements a SiFive S51 (64-bit RV64) core as a FPGA b...")
- 11:00, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive S21 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive S21 Standard Core Dev Kit. The SiFive S21 Standard Core Dev Kit implements a SiFive S21 (64-bit RV64) core as a FPGA b...")
- 10:59, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive E76 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive E76 Standard Core Dev Kit. The SiFive E76 Standard Core Dev Kit implements a SiFive E76 (32-bit RV32) core as a FPGA b...")
- 10:59, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive E34 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive E34 Standard Core Dev Kit. The SiFive E34 Standard Core Dev Kit implements a SiFive E34 (32-bit RV32) core as a FPGA b...")
- 10:59, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive E24 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive E24 Standard Core Dev Kit. The SiFive E24 Standard Core Dev Kit implements a SiFive E24 (32-bit RV32) core as a FPGA b...")
- 10:58, 26 May 2021 (diff | hist) . . (+3,762) . . N SiFive E21 Standard Core Dev Kit (Created page with "__TOC__ This article describes specifics for the SiFive E21 Standard Core Dev Kit. The SiFive E21 Standard Core Dev Kit implements a SiFive E21 (32-bit RV32) core as a FPGA b...")
- 10:56, 26 May 2021 (diff | hist) . . (+602) . . Debug Probes - J-Link & J-Trace (→SiFive)
- 10:54, 26 May 2021 (diff | hist) . . (+957) . . N SiFive S51 (Created page with "The SiFive S51 is a 64-bit (RV64) core of the SiFive S5 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The S51 and S51ARTY device sel...")
- 10:54, 26 May 2021 (diff | hist) . . (+993) . . N SiFive S21 (Created page with "The SiFive S21 is a 64-bit (RV64) core of the SiFive S2 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The S21 and S21ARTY device sel...")
- 10:53, 26 May 2021 (diff | hist) . . (+957) . . N SiFive S76 (Created page with "The SiFive S76 is a 64-bit (RV64) core of the SiFive S7 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The S76 and S76ARTY device sel...")
- 10:53, 26 May 2021 (diff | hist) . . (+957) . . N SiFive E76 (Created page with "The SiFive E76 is a 32-bit (RV32) core of the SiFive E7 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E76 and E76ARTY device sel...")
- 10:52, 26 May 2021 (diff | hist) . . (+957) . . N SiFive E34 (Created page with "The SiFive E34 is a 32-bit (RV32) core of the SiFive E3 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E34 and E34ARTY device sel...")
- 10:52, 26 May 2021 (diff | hist) . . (+993) . . N SiFive E24 (Created page with "The SiFive E24 is a 32-bit (RV32) core of the SiFive E2 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E24 and E24ARTY device sel...")
- 10:50, 26 May 2021 (diff | hist) . . (0) . . SiFive E21
- 10:49, 26 May 2021 (diff | hist) . . (+993) . . N SiFive E21 (Created page with "The SiFive E21 is a 64-bit (RV64) core of the SiFive E2 series cores, designed by SiFive. __TOC__ = Minimum required J-Link software version = The E21 and E21ARTY device sel...")