Difference between revisions of "Infineon CYT2B6"

From SEGGER Wiki
Jump to: navigation, search
(Created page with "'''CYT2B6 (TVII-B-E-512K)''' is a subfamily of Traveo II microcontrollers containing a Cortex M4 and Cortex M0+ CPU. == Flash memory lay...")
 
 
(7 intermediate revisions by 4 users not shown)
Line 1: Line 1:
−
'''CYT2B6 (TVII-B-E-512K)''' is a subfamily of [[Cypress Traveo II device family | Traveo II]] microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
 +
The Infineon '''CYT2B6 (TVII-B-E-512K)''' is a subfamily of the [[Infineon Traveo T2G]] microcontrollers containing a Cortex M4 and Cortex M0+ CPU.
   
  +
== SRAM ==
  +
The CYT2B6 family features 64 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used.
 
== Flash memory layout ==
  
== Flash memory layout ==
  +
The CYT2B6 series devices have 576 KiB Code flash and a 64 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
   
  +
{| class="seggertable"
−
The CYT2B6 series devices have 576 KB Code flash and a 64 KB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.
  
−  
−
{| class="wikitable"
  
 
|-
  
|-
 
! Flash !! Start adress !! End adress !! Sector size !! Sector count !! Total size
  
! Flash !! Start adress !! End adress !! Sector size !! Sector count !! Total size
 
|-
  
|-
−
| Code flash large area || 0x10000000 || 0x1006FFFF || 32 KB || 14 || 448 KB
 +
| Code flash large area || 0x10000000 || 0x1006FFFF || 32 KiB || 14 || 448 KiB
 
|-
  
|-
−
| Code flash small area || 0x10070000 || 0x1008FFFF || 8 KB || 16 || 128 KB
 +
| Code flash small area || 0x10070000 || 0x1008FFFF || 8 KiB || 16 || 128 KiB
 
|-
  
|-
−
| Work flash large area || 0x14000000 || 0x1400BFFF || 2 KB || 24 || 48 KB
 +
| Work flash large area || 0x14000000 || 0x1400BFFF || 2 KiB || 24 || 48 KiB
 
|-
  
|-
−
| Work flash small area || 0x1400C000 || 0x1400FFFF || 128 B || 128 || 16 KB
 +
| Work flash small area || 0x1400C000 || 0x1400FFFF || 128 B || 128 || 16 KiB
 
|}
  
|}
  +
{{Note|1=For information regarding Supervisory Flash (SFlash), please refer to [[Infineon_Traveo_T2G#Supervisory_Flash|Infineon Traveo T2G article]]}}
  +
  +
==Example Application==
  +
The following example projects were created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU inside. It is a simple Hello World sample linked into the internal flash.
  +
  +
'''SETUP'''
  +
*J-Link software: V7.52ba
  +
*Embedded Studio: V5.50d
  +
*Hardware: CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU
  +
*Link: [[File:Cypress_CYT2B65BAD_M0.zip]]
  +
*Link: [[File:Cypress_CYT2B65BAD_M4.zip]]

Latest revision as of 11:48, 20 October 2023

The Infineon CYT2B6 (TVII-B-E-512K) is a subfamily of the Infineon Traveo T2G microcontrollers containing a Cortex M4 and Cortex M0+ CPU.

SRAM

The CYT2B6 family features 64 KB of SRAM located at 0x08000000. The first 2 KB are reserved for internal usage and may not be used.

Flash memory layout

The CYT2B6 series devices have 576 KiB Code flash and a 64 KiB Work flash. Both flashes are split in an area of large sectors and an area of small sectors.

Flash Start adress End adress Sector size Sector count Total size
Code flash large area 0x10000000 0x1006FFFF 32 KiB 14 448 KiB
Code flash small area 0x10070000 0x1008FFFF 8 KiB 16 128 KiB
Work flash large area 0x14000000 0x1400BFFF 2 KiB 24 48 KiB
Work flash small area 0x1400C000 0x1400FFFF 128 B 128 16 KiB
Note:
For information regarding Supervisory Flash (SFlash), please refer to Infineon Traveo T2G article

Example Application

The following example projects were created with the SEGGER Embedded Studio project wizard and runs out-of-the-box on the CYTVII-B-E-1M-100-CPU Rev. 1.0 board with CYT2B65BADES MCU inside. It is a simple Hello World sample linked into the internal flash.

SETUP

Retrieved from "https://wiki.segger.com/index.php?title=Infineon_CYT2B6&oldid=16696"