Infineon Traveo T2G

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This article describes device specifics of the Infineon Traveo II device family.

Supervisory Flash

All Infineon Traveo T2G devices do provide a Supervisory Flash region (SFlash) located at 0x17000800. It is split in multiple writable and non-writable sections. J-Link does provide programming support for all writable sections.

Address region Description
0x17000800-0x17000FFF The user's area. 2 KB are used to store arbitrary data.
0x17001A00-0x17001A03 Normal Access Restrictions (NAR). Used for chip protection in the Normal Life Cycle stage.
0x17001A04-0x17001A07 Normal Dead Access Restrictions (NDAR). Used for chip protection in the Normal Dead Life Cycle stage.
0x17006400-0x17006FFF The Public Key. Used for a digital signature of the application.
0x17007600-0x170077FF Application protection settings.
0x17007C00-0x17007DFF The Table of contents, part 2 (TOC2). Used to locate OEM objects.


Note:
  • The Infineon Traveo T2G devices do not provide means to erase the SFlash regions. They may be re-programmed by simply programming them, without prior erase.
  • Programming of the supervisory Flash is only at specific areas possible. Writing outside the specific sub-regions is not possible at any Life Cycle stage except VIRGIN which is a factory-only stage.

Read Work Flash

Reading from work flash that is still in erased state will result in an error message, because of the nature of differential flash. Normal usage of work flash is as follows:

  1. Erase entire sector.
  2. Program word(s).
  3. Read 32-bit word.

Flash breakpoints

For Infineon Traveo II series devices the flash breakpoint feature may lead to hard-faults. This is due to the reason that it is mandatory to activate interrupts for flash programming on these devices. As a result interrupts like Systick timer can disrupt the flash programming routine and try to access flash areas themselves, which can lead to hard-faults.

Reset

J-Link does not perform a reset for the Cortex-M7 dual-cores, as the expected reset behavior highly depends on the use case.

  • System reset: Will reset the whole CPU (all cores), but may disable the other Cortex-M7 core unintentionally.
  • Core reset: Will only reset the Cortex-M7 connected to, but no other core, even though a full system reset might be expected.

If you require such a reset, please refer to the following sample J-Link script file. Search for USER SELECTION REQUIRED to find where to adjust the selected core / reset strategy.

Sub families

The Traveo II device family has the following sub families:

Device Codes / Ordering Codes

For the Traveo II family, there are two different name schemes used:

  • Device Codes (e.g. CYT2B63BAS)
  • Ordering Codes (e.g. CYT2B63BAD)

From J-Link perspective, the important difference is that the ordering code contains the silicon revision at the last position while the device code does not. The last position of the device code represents the temperature grade instead. Depending on the silicon revision, the J-Link software has to behave slightly different because the behavior of the flash ROM API has been changed between the silicon revisions. For the latest version, it does not matter if the device code or ordering code is selected as "device name" in the J-Link software because the ordering code always behaves compatible to the latest silicon revision. However, when using an older silicon revision, we recommend to use the ordering code instead of the device code as "device name".

Example CYT2B6 family

  1. Device Code: CYT2B63BAS / CYT2B63BAE (temperature grade S and E / revision unknown)
  2. Ordering Code: CYT2B63BAD (revision D)

FAQ

(Q1) What is the expected method for IDE to connect with M0 core and M4 or M7 core?

For M0 no special handling is needed. For M4 and M7 core avoid resets before connecting to the core as this might disable M4/M7 core.

(Q2) Is it possible to connect CYT2B63BAD_M4 only from J-Link Commander without connection to CYT2B63BAD_M0?

Yes connecting directly to M4/M7 is possible, as during our connect sequence J-Link connects to the M0 to enable M4/M7 core before connecting to M4/M7.