Difference between revisions of "Renesas RA6M5"
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The Renesas RA6M5 series are microcontrollers based on the ARM Cortex-M33 core. |
The Renesas RA6M5 series are microcontrollers based on the ARM Cortex-M33 core. |
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| − | =Flash= |
+ | ==Flash== |
| + | ===Internal option-setting memory=== |
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| − | The internal flash consists of a program region (maximum size 2048KB) and a data region (size 8KB). |
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| + | Option-settings memory is located at 0x0100A100 has a size of 512 Bytes. |
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| − | |||
| + | ===Internal program flash=== |
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| − | Furthermore, an optional external QSPI flash might be present (maximum size 64MB) |
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| + | The size of the program flash is dependent on the device used. |
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| − | |||
| + | {| class="wikitable" |
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| − | '''Note:''' Programming the flash regions is currently not supported in J-Flash. |
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| + | |- |
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| − | ==Supported Regions== |
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| + | ! Device !! Size (KiB) || Memory region |
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| − | The following regions are supported by the J-Link: |
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| + | |- |
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| − | *Program flash (0x00000000 up to 0x00200000) |
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| + | | R7FA6M5BF|| 1024 || 0x00000000 - 0x000FFFFF |
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| − | *Data flash (0x08000000 to 0x08002000) |
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| + | |- |
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| − | *Option-setting memory (0x0100A100 to 0x0100A300) |
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| + | | R7FA4M3AE|| 1536 || 0x00000000 - 0x0017FFFF |
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| − | *External QSPI flash (0x60000000 up to 0x64000000) |
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| + | |- |
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| + | | R7FA6M5AH<br>R7FA6M5BH|| 2048 || 0x00000000 - 0x001FFFFF |
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| + | |} |
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| + | {{Note|Currently only single bank flash operations are supported. Dual bank mode is not supported.}} |
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| + | ===Internal data flash=== |
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| + | Internal data flash is located at 0x08000000 has a size of 8 KB. |
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| + | ===External QSPI flash=== |
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| + | External QSPI flash is located at 0x60000000. |
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{{:Renesas RA6M4 flash loaders}} |
{{:Renesas RA6M4 flash loaders}} |
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| − | =Evaluation Boards= |
+ | ==Evaluation Boards== |
* [[Renesas EK-RA6M5]] |
* [[Renesas EK-RA6M5]] |
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| + | |||
| + | == Tracing on RA6M5 series == |
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| + | === Tracing on Renesas R7FA6M5 === |
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| + | ==== Minimum requirements ==== |
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| + | In order to use trace on the Renesas R7FA6M5 MCU devices, the following minimum requirements have to be met: |
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| + | * J-Link software version V7.92h or later |
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| + | * Ozone V3.30b or later (if streaming trace and / or the sample project from below shall be used) |
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| + | * SEGGER Embedded Studio V7.30 |
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| + | * J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace |
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| + | * J-Link Plus V12 or later for TMC/ETB trace |
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| + | To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary. |
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| + | |||
| + | ==== Streaming trace ==== |
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| + | The project has been tested with the minimum requirements mentioned above and a ''Renesas EK-RA6M5''. |
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| + | |||
| + | '''Example project:''' [[Media:Renesas_R7FA6M5_TracePins.zip | Renesas_R7FA6M5_TracePins.zip]] |
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| + | |||
| + | '''Note:''' The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/. |
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| + | |||
| + | To create your own .JLinkScriptfile you can use the following guide as reference: [[How_to_configure_JLinkScript_files_to_enable_tracing]] |
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| + | |||
| + | ==== Trace buffer (TMC/ETB) ==== |
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| + | '''Example Project:''' [[Media:Renesas_R7FA6M5_TraceBuffer.zip | Renesas_R7FA6M5_TraceBuffer.zip]] |
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| + | |||
| + | ==== Tested Hardware ==== |
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| + | [[File:EK_RA6M5.jpg|none|thumb|Renesas EK-RA6M5 evaluation board]] |
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| + | |||
| + | ==== Reference trace signal quality ==== |
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| + | The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. |
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| + | All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. |
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| + | If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. |
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| + | More information about correct trace timing can be found at the following [https://www.segger.com/products/debug-probes/j-trace/technology/setting-up-trace/ website]. |
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| + | |||
| + | ===== Trace clock signal quality ===== |
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| + | The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference. |
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| + | [[File:RA6M5_EK_Multiple_TCLK.png|none|thumb|Trace clock signal quality]] |
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| + | |||
| + | ===== Rise time ===== |
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| + | The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. |
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| + | For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal. |
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| + | [[File:RA6M5_EK_RiseTime_TCLK.png|none|thumb|TCLK rise time]] |
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| + | |||
| + | ===== Setup time ===== |
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| + | The setup time shows the relative setup time between a trace data signal and trace clock. |
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| + | The measurement markers are set at 50% of the expected voltage level respectively. |
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| + | The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal. |
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| + | [[File:RA6M5_EK_SetupTime_TD0.png|none|thumb|TD0 setup time]] |
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Latest revision as of 16:18, 20 October 2023
The Renesas RA6M5 series are microcontrollers based on the ARM Cortex-M33 core.
Flash
Internal option-setting memory
Option-settings memory is located at 0x0100A100 has a size of 512 Bytes.
Internal program flash
The size of the program flash is dependent on the device used.
| Device | Size (KiB) | Memory region |
|---|---|---|
| R7FA6M5BF | 1024 | 0x00000000 - 0x000FFFFF |
| R7FA4M3AE | 1536 | 0x00000000 - 0x0017FFFF |
| R7FA6M5AH R7FA6M5BH |
2048 | 0x00000000 - 0x001FFFFF |
Currently only single bank flash operations are supported. Dual bank mode is not supported.
Internal data flash
Internal data flash is located at 0x08000000 has a size of 8 KB.
External QSPI flash
External QSPI flash is located at 0x60000000.
Supported pin configurations
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
- CLK@P305_nCS@P306_D0@P307_D1@P503_D2@P104_D3@P505 (default)
- CLK@P500_nCS@P501_D0@P502_D1@P503_D2@P504_D3@P505
- CLK@P305_nCS@P306_D0@P307_D1@P308_D2@P309_D3@P310
Evaluation Boards
Tracing on RA6M5 series
Tracing on Renesas R7FA6M5
Minimum requirements
In order to use trace on the Renesas R7FA6M5 MCU devices, the following minimum requirements have to be met:
- J-Link software version V7.92h or later
- Ozone V3.30b or later (if streaming trace and / or the sample project from below shall be used)
- SEGGER Embedded Studio V7.30
- J-Trace PRO for Cortex-M HW version V3.0 or later for streaming trace
- J-Link Plus V12 or later for TMC/ETB trace
To rebuild the project our IDE Embedded Studio can be used. The recommended version to rebuild the projects is V6.30. But the examples are all prebuild and work out-of-the box with Ozone, so rebuilding is not necessary.
Streaming trace
The project has been tested with the minimum requirements mentioned above and a Renesas EK-RA6M5.
Example project: Renesas_R7FA6M5_TracePins.zip
Note: The example is shipped with a compiled .JLinkScriptfile, should you need the original source, please get in touch with SEGGER directly via our support system: https://www.segger.com/ticket/.
To create your own .JLinkScriptfile you can use the following guide as reference: How_to_configure_JLinkScript_files_to_enable_tracing
Trace buffer (TMC/ETB)
Example Project: Renesas_R7FA6M5_TraceBuffer.zip
Tested Hardware
Reference trace signal quality
The following pictures show oscilloscope measurements of trace signals output by the "Tested Hardware" using the example project. All measurements have been performed using a Agilent InfiniiVision DSO7034B 350 MHz 2GSa/s oscilloscope and 1156A 1.5 GHz Active Probes. If your trace signals look similar on your trace hardware, chances are good that tracing will work out-of-the-box using the example project. More information about correct trace timing can be found at the following website.
Trace clock signal quality
The trace clock signal quality shows multiple trace clock cycles on the tested hardware as reference.
Rise time
The rise time of a signal shows the time needed for a signal to rise from logical 0 to logical 1. For this the values at 10% and 90% of the expected voltage level get used as markers. The following picture shows such a measurement for the trace clock signal.
Setup time
The setup time shows the relative setup time between a trace data signal and trace clock. The measurement markers are set at 50% of the expected voltage level respectively. The following picture shows such a measurement for the trace data signal 0 relative to the trace clock signal.
