User contributions
(newest | oldest) View (newer 50 | older 50) (20 | 50 | 100 | 250 | 500)
- 12:57, 14 March 2023 (diff | hist) . . (+2,377) . . J-Link RISC-V (→JTAG chains)
- 12:02, 14 March 2023 (diff | hist) . . (+1,047) . . J-Link RISC-V (→RISC-V behind a CoreSight DAP)
- 10:52, 14 March 2023 (diff | hist) . . (+1,621) . . J-Link RISC-V
- 12:59, 8 March 2023 (diff | hist) . . (+300) . . GD32VF103
- 19:30, 2 March 2023 (diff | hist) . . (+1,918) . . J-Link zoned memory access
- 19:25, 2 March 2023 (diff | hist) . . (+3) . . N J-Link High-Speed Sampling (Created page with "TBD")
- 19:18, 2 March 2023 (diff | hist) . . (+4) . . Renesas RZ/T2M (→Zoned memory access)
- 19:17, 2 March 2023 (diff | hist) . . (+91) . . Renesas RZ/T2M (→Zoned memory access)
- 19:15, 2 March 2023 (diff | hist) . . (-14) . . Renesas RZ/T2M (→RTT)
- 19:15, 2 March 2023 (diff | hist) . . (-14) . . Renesas RZ/T2M (→HSS)
- 19:13, 2 March 2023 (diff | hist) . . (+597) . . Renesas RZ/T2M (→HSS)
- 19:06, 2 March 2023 (diff | hist) . . (+3) . . N J-Link zoned memory access (Created page with "TBD")
- 19:05, 2 March 2023 (diff | hist) . . (-8) . . Renesas RZ/T2M (→RTT support)
- 19:05, 2 March 2023 (diff | hist) . . (+8) . . Renesas RZ/T2M (→RTT)
- 19:04, 2 March 2023 (diff | hist) . . (+1,136) . . Renesas RZ/T2M (→Debug Authentication)
- 17:08, 23 February 2023 (diff | hist) . . (+415) . . J-Link Commander (→Write4)
- 17:06, 23 February 2023 (diff | hist) . . (+95) . . J-Link Commander (→Commands)
- 10:17, 15 February 2023 (diff | hist) . . (-32) . . Syntacore SCR4 (current)
- 10:17, 15 February 2023 (diff | hist) . . (-27) . . Syntacore SCR3 (current)
- 10:16, 15 February 2023 (diff | hist) . . (-36) . . Syntacore SCR3
- 17:38, 14 February 2023 (diff | hist) . . (+636) . . J-Link GDB Server (→-vd)
- 16:29, 14 February 2023 (diff | hist) . . (+931) . . N Syntacore SCR7 (Created page with "The Syntacore SCR7 is a 64-bit (RV64) core, designed by [https://syntacore.com Syntacore]. __TOC__ = Requirements = * A current J-Link model with RISC-V support * [https://w...") (current)
- 16:29, 14 February 2023 (diff | hist) . . (+931) . . N Syntacore SCR6 (Created page with "The Syntacore SCR6 is a 64-bit (RV64) core, designed by [https://syntacore.com Syntacore]. __TOC__ = Requirements = * A current J-Link model with RISC-V support * [https://w...") (current)
- 16:29, 14 February 2023 (diff | hist) . . (+948) . . N Syntacore SCR5 (Created page with "The Syntacore SCR5 is a 32-bit (RV32) or 64-bit (RV64) core, designed by [https://syntacore.com Syntacore]. __TOC__ = Requirements = * A current J-Link model with RISC-V sup...") (current)
- 16:28, 14 February 2023 (diff | hist) . . (+980) . . N Syntacore SCR4 (Created page with "The Syntacore SCR4 is a 32-bit (RV32) or 64-bit (RV64) core, designed by [https://syntacore.com/page/products/processor-ip/scr4 Syntacore]. __TOC__ = Requirements = * A curr...")
- 16:14, 14 February 2023 (diff | hist) . . (+112) . . Debug Probes - J-Link & J-Trace (→Syntacore)
- 18:18, 7 February 2023 (diff | hist) . . (+283) . . J-Flash SPI (→How to configure quad mode)
- 18:39, 14 December 2022 (diff | hist) . . (+9) . . J-Link ARMv8-AR (→EL2 registers)
- 18:36, 14 December 2022 (diff | hist) . . (+441) . . J-Link ARMv8-AR
- 10:21, 14 December 2022 (diff | hist) . . (-24) . . J-Link Eco mode (current)
- 10:20, 14 December 2022 (diff | hist) . . (0) . . m J-Link Eco mode (Alex moved page J-Link LPM to J-Link Eco mode: Renamed feature)
- 10:20, 14 December 2022 (diff | hist) . . (+29) . . N J-Link LPM (Alex moved page J-Link LPM to J-Link Eco mode: Renamed feature) (current) (Tag: New redirect)
- 15:15, 7 December 2022 (diff | hist) . . (+27) . . J-Link ARMv8-AR (→EL2 registers)
- 15:13, 7 December 2022 (diff | hist) . . (+1,453) . . N J-Link ARMv8-AR (Created page with "This article describes the debugging specifics for ARMv8-A/R based chips & cores. __TOC__ == Debugging through execution state changes == The ARMv8-A/R architecture describe...")
- 15:03, 7 December 2022 (diff | hist) . . (+34) . . Debug Probes - J-Link & J-Trace (→Core specifics)
- 16:04, 5 December 2022 (diff | hist) . . (+1,201) . . J-Link script files (→ResetTarget())
- 15:57, 5 December 2022 (diff | hist) . . (+185) . . J-Link script files (→InitTarget())
- 09:41, 30 November 2022 (diff | hist) . . (-22) . . Debug Probes - J-Link & J-Trace (→J-Link hardware)
- 15:14, 29 November 2022 (diff | hist) . . (+565) . . N J-Link Eco mode (Created page with "J-Link low power mode (LPM) support refers to a J-Link unit supporting to run in different low power modes.<br> It is '''not related''' to (and must not be confused with) low...")
- 11:35, 14 November 2022 (diff | hist) . . (+559) . . J-Link drag and drop programming (→Download of large data files)
- 12:27, 9 November 2022 (diff | hist) . . (+88) . . Debug Probes - J-Link & J-Trace (→Codasip)
- 12:25, 9 November 2022 (diff | hist) . . (+1) . . Codasip L31 (→Minimum required J-Link software version)
- 12:25, 9 November 2022 (diff | hist) . . (+565) . . N Codasip L11 (Created page with "The Codasip L11 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. __TOC__ = Minimum required J-Link software version =...")
- 12:22, 9 November 2022 (diff | hist) . . (+636) . . N Codasip L31 (Created page with "The Codasip L31 is a 32-bit (RV32) core, designed by [https://codasip.com/products/codasip-risc-v-processors/ Codasip]. It is available in 2 variants: * L31 (no FPU) * L31F (i...")
- 17:51, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-K22-CortexA (→Drag and drop programming support)
- 17:50, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-K22-CortexM (→Drag and drop programming support)
- 17:50, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-K22-SiFive (→Drag and drop programming support) (current)
- 17:50, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-nRF5340-NordicSemi (current)
- 17:50, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-SAM3U-NordicSemi (current)
- 17:49, 7 November 2022 (diff | hist) . . (+311) . . J-Link-OB-K22-NordicSemi (current)