Difference between revisions of "Xilinx Zynq-7000"
(Created page with "TBD") |
|||
Line 1: | Line 1: | ||
+ | __TOC__ |
||
− | TBD |
||
+ | The '''Xilinx Zynq-7000''' are Cortex-A9 based microcontrollers |
||
+ | |||
+ | ==Flash Banks== |
||
+ | ===QSPI Flash=== |
||
+ | QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the [[QSPI Flash Programming Support | QSPI Flash Programming Support article]].<br> |
||
+ | J-Link supports QSPI programming for Zynq-7000 for the flash bank located at 0xFC000000. There are multiple loaders available. The default loader assumes that an external osciallator running at 33 MHz is used and uses this as a base clock for the PLL to run the flash programming at 50 MHz. If you are using an oscillator that is running faster than 33 MHz, we recommend using the NoPLLInit loader. Otherwise proper execution of the flash operation is not guaranteed. |
||
+ | {| class="seggertable" |
||
+ | |- |
||
+ | ! Device !! Base address !! Maximum size || Available loaders |
||
+ | |- |
||
+ | | XA7Z010<br>XA7Z020<br>XC7Z007S<br>XC7Z012S<br>XC7Z014S<br>XC7Z010<br>XC7Z015<br>XC7Z020<br>XC7Z030<br>XC7Z035<br>XC7Z045<br>XC7Z100<br>XQ7Z020 || 0xFC000000 || 16 MB || |
||
+ | *'''Default''' |
||
+ | *NoPLLInit |
||
+ | |} |
||
+ | |||
+ | ==Device Specifc Handling== |
||
+ | ===Reset=== |
||
+ | *The devices uses normal Cortex-A reset, no special handling necessary, like described [[J-Link_Reset_Strategies#Type_0:_Normal_2 | here]]. |
||
+ | |||
+ | ==Evaluation Boards== |
||
+ | *Xilinx ZedBoard evaluation board: https://wiki.segger.com/Zedboard_Evalboard |
||
+ | *Xilinx MicroZed evaluation board: https://wiki.segger.com/MicroZed_Evalboard |
Revision as of 17:27, 19 January 2023
The Xilinx Zynq-7000 are Cortex-A9 based microcontrollers
Flash Banks
QSPI Flash
QSPI flash programming requires special handling compared to internal flash. For more information about this, please see the QSPI Flash Programming Support article.
J-Link supports QSPI programming for Zynq-7000 for the flash bank located at 0xFC000000. There are multiple loaders available. The default loader assumes that an external osciallator running at 33 MHz is used and uses this as a base clock for the PLL to run the flash programming at 50 MHz. If you are using an oscillator that is running faster than 33 MHz, we recommend using the NoPLLInit loader. Otherwise proper execution of the flash operation is not guaranteed.
Device | Base address | Maximum size | Available loaders |
---|---|---|---|
XA7Z010 XA7Z020 XC7Z007S XC7Z012S XC7Z014S XC7Z010 XC7Z015 XC7Z020 XC7Z030 XC7Z035 XC7Z045 XC7Z100 XQ7Z020 |
0xFC000000 | 16 MB |
|
Device Specifc Handling
Reset
- The devices uses normal Cortex-A reset, no special handling necessary, like described here.
Evaluation Boards
- Xilinx ZedBoard evaluation board: https://wiki.segger.com/Zedboard_Evalboard
- Xilinx MicroZed evaluation board: https://wiki.segger.com/MicroZed_Evalboard