User contributions
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- 10:51, 15 July 2022 (diff | hist) . . (+152) . . J-Link Cortex-M application uses cycle counter (current)
- 10:50, 15 July 2022 (diff | hist) . . (-4) . . J-Link Cortex-M application uses cycle counter
- 10:49, 15 July 2022 (diff | hist) . . (+1,552) . . N J-Link Cortex-M application uses cycle counter (Created page with "The ARM Cortex-M cores provide a cycle counter as part of the Data Watchpoint and Trace unit (DWT) which is a debug unit of the Cortex-M cores. {{Note | 1=J-Link assumes that...")
- 10:32, 15 July 2022 (diff | hist) . . (+146) . . J-Link Command Strings (→List of available commands)
- 10:31, 15 July 2022 (diff | hist) . . (+892) . . J-Link Command Strings (→SetSkipProgOnCRCMatch)
- 10:22, 15 July 2022 (diff | hist) . . (-27) . . J-Link Command Strings (→SetDbgPowerDownOnClose)
- 10:12, 15 July 2022 (diff | hist) . . (+48) . . Debug Probes - J-Link & J-Trace (→Troubleshooting)
- 10:12, 15 July 2022 (diff | hist) . . (+53) . . Debug Probes - J-Link & J-Trace (→Troubleshooting)
- 21:51, 13 July 2022 (diff | hist) . . (0) . . SEGGER Flash Loader (→JLinkDevices folder)
- 17:41, 13 July 2022 (diff | hist) . . (0) . . m J-Link ST SR5E1 (Alex moved page J-Link ST SR5E1 series to J-Link ST SR5E1)
- 17:41, 13 July 2022 (diff | hist) . . (+29) . . N J-Link ST SR5E1 series (Alex moved page J-Link ST SR5E1 series to J-Link ST SR5E1) (current) (Tag: New redirect)
- 17:41, 13 July 2022 (diff | hist) . . (-14) . . Debug Probes - J-Link & J-Trace (→ST)
- 17:40, 13 July 2022 (diff | hist) . . (+199) . . J-Link ST SR5E1
- 16:21, 13 July 2022 (diff | hist) . . (-1) . . DAP (→DAP topology examples =)
- 16:19, 13 July 2022 (diff | hist) . . (0) . . DAP (→DAP topology example - Cascaded APs)
- 16:19, 13 July 2022 (diff | hist) . . (+467) . . DAP (→DAP topology examples)
- 16:19, 13 July 2022 (diff | hist) . . (0) . . N File:DAP CascadedAPs CortexM System.vsdx (current)
- 16:18, 13 July 2022 (diff | hist) . . (0) . . N File:DAP CascadedAPs CortexM System.png (current)
- 11:44, 12 July 2022 (diff | hist) . . (+1) . . Debug Probes - J-Link & J-Trace (→NXP)
- 11:43, 12 July 2022 (diff | hist) . . (+32) . . Debug Probes - J-Link & J-Trace (→NXP)
- 09:03, 12 July 2022 (diff | hist) . . (+3) . . N J-Link ST SR5E1 (Created page with "TBD")
- 09:02, 12 July 2022 (diff | hist) . . (+44) . . Debug Probes - J-Link & J-Trace (→Device specifics)
- 10:07, 7 July 2022 (diff | hist) . . (+6) . . J-Link-OB-K22-CortexM (→SN 900031732 to 900032331)
- 10:07, 7 July 2022 (diff | hist) . . (+155) . . J-Link-OB-K22-CortexM
- 10:05, 7 July 2022 (diff | hist) . . (+1) . . Debug Probes - J-Link & J-Trace (→J-Link model specifics)
- 10:05, 7 July 2022 (diff | hist) . . (0) . . N File:JLink-OB-K22-CortexM 900031732 to 900032331 VCOMPort.png (current)
- 10:05, 7 July 2022 (diff | hist) . . (0) . . N File:JLink-OB-K22-CortexM 900031732 to 900032331 AutoCorrect.png (current)
- 10:02, 7 July 2022 (diff | hist) . . (-11) . . J-Link-OB-K22-CortexM
- 10:00, 7 July 2022 (diff | hist) . . (+722) . . N J-Link-OB-K22-CortexM (Created page with "This article describes specifics of the J-Link OB CortexM (See https://www.segger.com/products/debug-probes/j-link/models/j-link-ob/#model-overview-supported-cores). __TOC__...")
- 09:14, 7 July 2022 (diff | hist) . . (+52) . . Debug Probes - J-Link & J-Trace (→J-Link model specifics)
- 09:45, 6 July 2022 (diff | hist) . . (+41) . . N J-Link Xtensa specifics (Created page with "__TOC__ TBD == Data breakpoints == TBD")
- 09:44, 6 July 2022 (diff | hist) . . (+39) . . Debug Probes - J-Link & J-Trace (→Core specifics)
- 17:01, 28 June 2022 (diff | hist) . . (+9) . . J-Link-OB-S124-Renesas (current)
- 17:00, 28 June 2022 (diff | hist) . . (+563) . . N J-Link-OB-S124-Renesas (Created page with "Several Renesas evaluation boards come with a J-Link-OB-S124-Renesas on them which allows out-of-the-box debugging on these boards without an external J-Link being connected....")
- 16:56, 28 June 2022 (diff | hist) . . (+54) . . Debug Probes - J-Link & J-Trace (→J-Link model specifics)
- 10:50, 21 June 2022 (diff | hist) . . (+1,000) . . J-Link cJTAG specifics
- 09:42, 2 June 2022 (diff | hist) . . (+659) . . N NXP MIMXRT685-EVK (Created page with "== J-Link OB == The NXP MIMXRT685-EVK comes with an LPC-Link2-on-board that can be reprogrammed via [https://www.nxp.com/lpcscrypt NXP LPCScrypt] to a J-Link OB. In order to...")
- 09:38, 2 June 2022 (diff | hist) . . (+40) . . Debug Probes - J-Link & J-Trace (→NXP)
- 09:13, 9 May 2022 (diff | hist) . . (+8) . . SEGGER Flash Loader (→Open Flashloader)
- 09:12, 9 May 2022 (diff | hist) . . (+602) . . SEGGER Flash Loader (→Open Flashloader)
- 10:47, 3 May 2022 (diff | hist) . . (+404) . . N J-Link-OB-K22-NordicSemi (Created page with "This J-Link on-board (OB) is a special version of the J-Link OB that is mounted on many eval boards from Nordic Semiconductor. == WinUSB support == This J-Link OB only suppor...")
- 10:47, 3 May 2022 (diff | hist) . . (+58) . . Debug Probes - J-Link & J-Trace (→J-Link model specifics)
- 10:25, 3 May 2022 (diff | hist) . . (+404) . . N J-Link-OB-nRF5340-NordicSemi (Created page with "This J-Link on-board (OB) is a special version of the J-Link OB that is mounted on many eval boards from Nordic Semiconductor. == WinUSB support == This J-Link OB only suppor...")
- 10:24, 3 May 2022 (diff | hist) . . (+404) . . N J-Link-OB-SAM3U-NordicSemi (Created page with "This J-Link on-board (OB) is a special version of the J-Link OB that is mounted on many eval boards from Nordic Semiconductor. == WinUSB support == This J-Link OB only suppor...")
- 10:09, 3 May 2022 (diff | hist) . . (+128) . . Debug Probes - J-Link & J-Trace (→J-Link model specifics)
- 10:10, 17 December 2021 (diff | hist) . . (+161) . . J-Link on Windows ARM (→Requirements)
- 11:33, 9 December 2021 (diff | hist) . . (+9) . . emIDE (current)
- 18:30, 6 December 2021 (diff | hist) . . (+24) . . Delayed Program Start in Debug (→Problem) (current)
- 18:29, 6 December 2021 (diff | hist) . . (+1,087) . . Delayed Program Start in Debug (→Problem)
- 12:18, 29 November 2021 (diff | hist) . . (+1,041) . . N J-Link NEORV32 (Created page with "The [https://www.neorv32.org/ NEORV32] is an free and open-source RV32 based RISC-V CPU that is supported by J-Link. In addition to this article, the generic RISC-V specifics...") (current)